
IO_Tile_1_17

 (3 1)  (45 273)  (45 273)  IO control bit: IOUP_REN_1

 (3 9)  (45 281)  (45 281)  IO control bit: IOUP_IE_0

 (1 11)  (43 282)  (43 282)  Enable bit of Mux _out_links/OutMux6_2 => wire_io_cluster/io_1/D_IN_0 span4_horz_r_2
 (17 13)  (23 285)  (23 285)  IOB_1 IO Functioning bit


IO_Tile_2_17

 (3 1)  (99 273)  (99 273)  IO control bit: IOUP_REN_1

 (3 9)  (99 281)  (99 281)  IO control bit: IOUP_IE_0

 (1 11)  (97 282)  (97 282)  Enable bit of Mux _out_links/OutMux6_2 => wire_io_cluster/io_1/D_IN_0 span4_horz_r_2
 (17 13)  (77 285)  (77 285)  IOB_1 IO Functioning bit


IO_Tile_3_17

 (3 1)  (153 273)  (153 273)  IO control bit: IOUP_REN_1

 (3 9)  (153 281)  (153 281)  IO control bit: IOUP_IE_0

 (1 11)  (151 282)  (151 282)  Enable bit of Mux _out_links/OutMux6_2 => wire_io_cluster/io_1/D_IN_0 span4_horz_r_2
 (17 13)  (131 285)  (131 285)  IOB_1 IO Functioning bit


IO_Tile_4_17

 (3 1)  (195 273)  (195 273)  IO control bit: IOUP_REN_1

 (0 3)  (191 274)  (191 274)  Enable bit of Mux _out_links/OutMux5_0 => wire_io_cluster/io_0/D_IN_0 span4_vert_40
 (17 3)  (173 274)  (173 274)  IOB_0 IO Functioning bit
 (2 6)  (194 279)  (194 279)  IO control bit: IOUP_REN_0

 (1 11)  (193 282)  (193 282)  Enable bit of Mux _out_links/OutMux6_2 => wire_io_cluster/io_1/D_IN_0 span4_horz_r_2
 (17 13)  (173 285)  (173 285)  IOB_1 IO Functioning bit


IO_Tile_5_17

 (3 1)  (249 273)  (249 273)  IO control bit: IOUP_REN_1

 (1 3)  (247 274)  (247 274)  Enable bit of Mux _out_links/OutMux6_0 => wire_io_cluster/io_0/D_IN_0 span4_horz_r_0
 (17 3)  (227 274)  (227 274)  IOB_0 IO Functioning bit
 (2 6)  (248 279)  (248 279)  IO control bit: IOUP_REN_0

 (14 7)  (258 278)  (258 278)  routing T_5_17.span4_horz_l_14 <X> T_5_17.span4_horz_r_2
 (0 11)  (245 282)  (245 282)  Enable bit of Mux _out_links/OutMux5_2 => wire_io_cluster/io_1/D_IN_0 span4_vert_44
 (17 13)  (227 285)  (227 285)  IOB_1 IO Functioning bit


IO_Tile_6_17

 (3 1)  (303 273)  (303 273)  IO control bit: GIOUP1_REN_1

 (0 3)  (299 274)  (299 274)  Enable bit of Mux _out_links/OutMux5_0 => wire_io_cluster/io_0/D_IN_0 span4_vert_40
 (17 3)  (281 274)  (281 274)  IOB_0 IO Functioning bit
 (2 6)  (302 279)  (302 279)  IO control bit: GIOUP1_REN_0

 (14 7)  (312 278)  (312 278)  routing T_6_17.span4_horz_l_14 <X> T_6_17.span4_horz_r_2
 (0 11)  (299 282)  (299 282)  Enable bit of Mux _out_links/OutMux5_2 => wire_io_cluster/io_1/D_IN_0 span4_vert_44
 (17 13)  (281 285)  (281 285)  IOB_1 IO Functioning bit


IO_Tile_7_17

 (0 3)  (357 274)  (357 274)  Enable bit of Mux _out_links/OutMux5_0 => wire_io_cluster/io_0/D_IN_0 span4_vert_40
 (17 3)  (339 274)  (339 274)  IOB_0 IO Functioning bit
 (2 6)  (360 279)  (360 279)  IO control bit: GIOUP0_REN_0

 (3 6)  (361 279)  (361 279)  IO control bit: GIOUP0_IE_1

 (14 7)  (370 278)  (370 278)  routing T_7_17.span4_horz_l_14 <X> T_7_17.span4_horz_r_2


IO_Tile_8_17

 (3 1)  (415 273)  (415 273)  IO control bit: BIOUP_REN_1

 (1 2)  (413 275)  (413 275)  Enable bit of Mux _out_links/OutMux8_0 => wire_io_cluster/io_0/D_IN_0 span4_horz_r_8
 (17 3)  (393 274)  (393 274)  IOB_0 IO Functioning bit
 (2 6)  (414 279)  (414 279)  IO control bit: BIOUP_REN_0

 (11 7)  (421 278)  (421 278)  routing T_8_17.span4_horz_l_14 <X> T_8_17.span4_vert_37
 (1 8)  (413 280)  (413 280)  Enable bit of Mux _out_links/OutMux3_2 => wire_io_cluster/io_1/D_IN_0 span4_vert_28
 (17 13)  (393 285)  (393 285)  IOB_1 IO Functioning bit


IO_Tile_9_17

 (3 1)  (469 273)  (469 273)  IO control bit: IOUP_REN_1

 (14 1)  (478 273)  (478 273)  routing T_9_17.span4_horz_l_12 <X> T_9_17.span4_horz_r_0
 (1 2)  (467 275)  (467 275)  Enable bit of Mux _out_links/OutMux8_0 => wire_io_cluster/io_0/D_IN_0 span4_horz_r_8
 (17 3)  (447 274)  (447 274)  IOB_0 IO Functioning bit
 (2 6)  (468 279)  (468 279)  IO control bit: IOUP_REN_0

 (14 7)  (478 278)  (478 278)  routing T_9_17.span4_horz_l_14 <X> T_9_17.span4_horz_r_2
 (16 8)  (446 280)  (446 280)  Enable bit of Mux _out_links/OutMuxc_2 => wire_io_cluster/io_1/D_IN_0 span12_vert_20
 (17 13)  (447 285)  (447 285)  IOB_1 IO Functioning bit


IO_Tile_10_17

 (0 0)  (519 272)  (519 272)  Enable bit of Mux _out_links/OutMux2_0 => wire_io_cluster/io_0/D_IN_0 span4_vert_16
 (3 1)  (523 273)  (523 273)  IO control bit: IOUP_REN_1

 (11 1)  (529 273)  (529 273)  routing T_10_17.span4_horz_l_12 <X> T_10_17.span4_vert_25
 (17 3)  (501 274)  (501 274)  IOB_0 IO Functioning bit
 (2 6)  (522 279)  (522 279)  IO control bit: IOUP_REN_0

 (14 6)  (532 279)  (532 279)  routing T_10_17.span4_horz_l_14 <X> T_10_17.span4_vert_13
 (0 8)  (519 280)  (519 280)  Enable bit of Mux _out_links/OutMux2_2 => wire_io_cluster/io_1/D_IN_0 span4_vert_20
 (17 13)  (501 285)  (501 285)  IOB_1 IO Functioning bit


IO_Tile_11_17

 (14 0)  (574 272)  (574 272)  routing T_11_17.span4_horz_l_12 <X> T_11_17.span4_vert_1
 (3 1)  (565 273)  (565 273)  IO control bit: IOUP_REN_1

 (14 6)  (574 279)  (574 279)  routing T_11_17.span4_horz_l_14 <X> T_11_17.span4_vert_13
 (0 9)  (561 281)  (561 281)  Enable bit of Mux _out_links/OutMux0_2 => wire_io_cluster/io_1/D_IN_0 span4_vert_4
 (3 9)  (565 281)  (565 281)  IO control bit: IOUP_IE_0

 (17 13)  (543 285)  (543 285)  IOB_1 IO Functioning bit


IO_Tile_12_17

 (2 1)  (618 273)  (618 273)  Enable bit of Mux _out_links/OutMux4_0 => wire_io_cluster/io_0/D_IN_0 span4_vert_32
 (3 1)  (619 273)  (619 273)  IO control bit: IOUP_REN_1

 (17 3)  (597 274)  (597 274)  IOB_0 IO Functioning bit
 (2 6)  (618 279)  (618 279)  IO control bit: IOUP_REN_0

 (1 10)  (617 283)  (617 283)  Enable bit of Mux _out_links/OutMux8_2 => wire_io_cluster/io_1/D_IN_0 span4_horz_r_10
 (17 13)  (597 285)  (597 285)  IOB_1 IO Functioning bit


IO_Tile_0_16

 (3 6)  (14 262)  (14 262)  IO control bit: IOLEFT_IE_1

 (3 9)  (14 265)  (14 265)  IO control bit: IOLEFT_IE_0



RAM_Tile_3_16

 (3 8)  (129 264)  (129 264)  routing T_3_16.sp12_h_r_1 <X> T_3_16.sp12_v_b_1
 (3 9)  (129 265)  (129 265)  routing T_3_16.sp12_h_r_1 <X> T_3_16.sp12_v_b_1


LogicTile_4_16

 (10 12)  (178 268)  (178 268)  routing T_4_16.sp4_v_t_40 <X> T_4_16.sp4_h_r_10


LogicTile_5_16

 (5 12)  (227 268)  (227 268)  routing T_5_16.sp4_v_t_44 <X> T_5_16.sp4_h_r_9


LogicTile_6_16

 (13 1)  (289 257)  (289 257)  routing T_6_16.sp4_v_t_44 <X> T_6_16.sp4_h_r_2
 (12 4)  (288 260)  (288 260)  routing T_6_16.sp4_v_t_40 <X> T_6_16.sp4_h_r_5


LogicTile_7_16

 (12 4)  (346 260)  (346 260)  routing T_7_16.sp4_v_t_40 <X> T_7_16.sp4_h_r_5


LogicTile_8_16

 (13 5)  (401 261)  (401 261)  routing T_8_16.sp4_v_t_37 <X> T_8_16.sp4_h_r_5
 (8 12)  (396 268)  (396 268)  routing T_8_16.sp4_h_l_47 <X> T_8_16.sp4_h_r_10


LogicTile_9_16

 (11 5)  (453 261)  (453 261)  routing T_9_16.sp4_h_l_44 <X> T_9_16.sp4_h_r_5
 (13 5)  (455 261)  (455 261)  routing T_9_16.sp4_h_l_44 <X> T_9_16.sp4_h_r_5


RAM_Tile_10_16

 (7 0)  (503 256)  (503 256)  Ram config bit: MEMT_bram_cbit_1

 (26 0)  (522 256)  (522 256)  routing T_10_16.lc_trk_g1_5 <X> T_10_16.input0_0
 (7 1)  (503 257)  (503 257)  Ram config bit: MEMT_bram_cbit_0

 (17 1)  (513 257)  (513 257)  Enable bit of Mux _local_links/g0_mux_0 => sp4_r_v_b_24 lc_trk_g0_0
 (27 1)  (523 257)  (523 257)  routing T_10_16.lc_trk_g1_5 <X> T_10_16.input0_0
 (29 1)  (525 257)  (525 257)  Enable bit of Mux _bram/lcb0_0 => lc_trk_g1_5 input0_0
 (32 1)  (528 257)  (528 257)  Enable bit of Mux _bram/lcb2_0 => lc_trk_g2_0 input2_0
 (33 1)  (529 257)  (529 257)  routing T_10_16.lc_trk_g2_0 <X> T_10_16.input2_0
 (1 2)  (497 258)  (497 258)  routing T_10_16.glb_netwk_4 <X> T_10_16.wire_bram/ram/RCLK
 (2 2)  (498 258)  (498 258)  Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_bram/ram/RCLK
 (7 2)  (503 258)  (503 258)  Ram config bit: MEMT_bram_cbit_3

 (15 2)  (511 258)  (511 258)  routing T_10_16.sp4_h_r_5 <X> T_10_16.lc_trk_g0_5
 (16 2)  (512 258)  (512 258)  routing T_10_16.sp4_h_r_5 <X> T_10_16.lc_trk_g0_5
 (17 2)  (513 258)  (513 258)  Enable bit of Mux _local_links/g0_mux_5 => sp4_h_r_5 lc_trk_g0_5
 (35 2)  (531 258)  (531 258)  routing T_10_16.lc_trk_g3_4 <X> T_10_16.input2_1
 (7 3)  (503 259)  (503 259)  Ram config bit: MEMT_bram_cbit_2

 (18 3)  (514 259)  (514 259)  routing T_10_16.sp4_h_r_5 <X> T_10_16.lc_trk_g0_5
 (27 3)  (523 259)  (523 259)  routing T_10_16.lc_trk_g3_0 <X> T_10_16.input0_1
 (28 3)  (524 259)  (524 259)  routing T_10_16.lc_trk_g3_0 <X> T_10_16.input0_1
 (29 3)  (525 259)  (525 259)  Enable bit of Mux _bram/lcb0_1 => lc_trk_g3_0 input0_1
 (32 3)  (528 259)  (528 259)  Enable bit of Mux _bram/lcb2_1 => lc_trk_g3_4 input2_1
 (33 3)  (529 259)  (529 259)  routing T_10_16.lc_trk_g3_4 <X> T_10_16.input2_1
 (34 3)  (530 259)  (530 259)  routing T_10_16.lc_trk_g3_4 <X> T_10_16.input2_1
 (7 4)  (503 260)  (503 260)  Cascade buffer Enable bit: MEMT_LC01_inmux00_bram_cbit_5

 (12 4)  (508 260)  (508 260)  routing T_10_16.sp4_h_l_39 <X> T_10_16.sp4_h_r_5
 (14 4)  (510 260)  (510 260)  routing T_10_16.sp4_h_l_5 <X> T_10_16.lc_trk_g1_0
 (15 4)  (511 260)  (511 260)  routing T_10_16.sp4_h_r_1 <X> T_10_16.lc_trk_g1_1
 (16 4)  (512 260)  (512 260)  routing T_10_16.sp4_h_r_1 <X> T_10_16.lc_trk_g1_1
 (17 4)  (513 260)  (513 260)  Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1
 (21 4)  (517 260)  (517 260)  routing T_10_16.sp4_v_b_11 <X> T_10_16.lc_trk_g1_3
 (22 4)  (518 260)  (518 260)  Enable bit of Mux _local_links/g1_mux_3 => sp4_v_b_11 lc_trk_g1_3
 (23 4)  (519 260)  (519 260)  routing T_10_16.sp4_v_b_11 <X> T_10_16.lc_trk_g1_3
 (13 5)  (509 261)  (509 261)  routing T_10_16.sp4_h_l_39 <X> T_10_16.sp4_h_r_5
 (14 5)  (510 261)  (510 261)  routing T_10_16.sp4_h_l_5 <X> T_10_16.lc_trk_g1_0
 (15 5)  (511 261)  (511 261)  routing T_10_16.sp4_h_l_5 <X> T_10_16.lc_trk_g1_0
 (16 5)  (512 261)  (512 261)  routing T_10_16.sp4_h_l_5 <X> T_10_16.lc_trk_g1_0
 (17 5)  (513 261)  (513 261)  Enable bit of Mux _local_links/g1_mux_0 => sp4_h_l_5 lc_trk_g1_0
 (18 5)  (514 261)  (514 261)  routing T_10_16.sp4_h_r_1 <X> T_10_16.lc_trk_g1_1
 (21 5)  (517 261)  (517 261)  routing T_10_16.sp4_v_b_11 <X> T_10_16.lc_trk_g1_3
 (26 5)  (522 261)  (522 261)  routing T_10_16.lc_trk_g2_2 <X> T_10_16.input0_2
 (28 5)  (524 261)  (524 261)  routing T_10_16.lc_trk_g2_2 <X> T_10_16.input0_2
 (29 5)  (525 261)  (525 261)  Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_2 input0_2
 (32 5)  (528 261)  (528 261)  Enable bit of Mux _bram/lcb2_2 => lc_trk_g0_0 input2_2
 (7 6)  (503 262)  (503 262)  Cascade buffer Enable bit: MEMT_LC04_inmux00_bram_cbit_7

 (15 6)  (511 262)  (511 262)  routing T_10_16.sp4_h_r_13 <X> T_10_16.lc_trk_g1_5
 (16 6)  (512 262)  (512 262)  routing T_10_16.sp4_h_r_13 <X> T_10_16.lc_trk_g1_5
 (17 6)  (513 262)  (513 262)  Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_13 lc_trk_g1_5
 (18 6)  (514 262)  (514 262)  routing T_10_16.sp4_h_r_13 <X> T_10_16.lc_trk_g1_5
 (26 6)  (522 262)  (522 262)  routing T_10_16.lc_trk_g2_5 <X> T_10_16.input0_3
 (27 6)  (523 262)  (523 262)  routing T_10_16.lc_trk_g3_7 <X> T_10_16.wire_bram/ram/WDATA_11
 (28 6)  (524 262)  (524 262)  routing T_10_16.lc_trk_g3_7 <X> T_10_16.wire_bram/ram/WDATA_11
 (29 6)  (525 262)  (525 262)  Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_7 wire_bram/ram/WDATA_11
 (30 6)  (526 262)  (526 262)  routing T_10_16.lc_trk_g3_7 <X> T_10_16.wire_bram/ram/WDATA_11
 (37 6)  (533 262)  (533 262)  Enable bit of Mux _out_links/OutMux5_3 => wire_bram/ram/RDATA_11 sp12_h_l_13
 (28 7)  (524 263)  (524 263)  routing T_10_16.lc_trk_g2_5 <X> T_10_16.input0_3
 (29 7)  (525 263)  (525 263)  Enable bit of Mux _bram/lcb0_3 => lc_trk_g2_5 input0_3
 (30 7)  (526 263)  (526 263)  routing T_10_16.lc_trk_g3_7 <X> T_10_16.wire_bram/ram/WDATA_11
 (14 8)  (510 264)  (510 264)  routing T_10_16.sp4_h_l_29 <X> T_10_16.lc_trk_g2_0
 (25 8)  (521 264)  (521 264)  routing T_10_16.sp4_h_r_34 <X> T_10_16.lc_trk_g2_2
 (14 9)  (510 265)  (510 265)  routing T_10_16.sp4_h_l_29 <X> T_10_16.lc_trk_g2_0
 (15 9)  (511 265)  (511 265)  routing T_10_16.sp4_h_l_29 <X> T_10_16.lc_trk_g2_0
 (16 9)  (512 265)  (512 265)  routing T_10_16.sp4_h_l_29 <X> T_10_16.lc_trk_g2_0
 (17 9)  (513 265)  (513 265)  Enable bit of Mux _local_links/g2_mux_0 => sp4_h_l_29 lc_trk_g2_0
 (22 9)  (518 265)  (518 265)  Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_34 lc_trk_g2_2
 (23 9)  (519 265)  (519 265)  routing T_10_16.sp4_h_r_34 <X> T_10_16.lc_trk_g2_2
 (24 9)  (520 265)  (520 265)  routing T_10_16.sp4_h_r_34 <X> T_10_16.lc_trk_g2_2
 (27 9)  (523 265)  (523 265)  routing T_10_16.lc_trk_g1_1 <X> T_10_16.input0_4
 (29 9)  (525 265)  (525 265)  Enable bit of Mux _bram/lcb0_4 => lc_trk_g1_1 input0_4
 (14 10)  (510 266)  (510 266)  routing T_10_16.sp4_v_b_28 <X> T_10_16.lc_trk_g2_4
 (15 10)  (511 266)  (511 266)  routing T_10_16.sp4_h_l_16 <X> T_10_16.lc_trk_g2_5
 (16 10)  (512 266)  (512 266)  routing T_10_16.sp4_h_l_16 <X> T_10_16.lc_trk_g2_5
 (17 10)  (513 266)  (513 266)  Enable bit of Mux _local_links/g2_mux_5 => sp4_h_l_16 lc_trk_g2_5
 (16 11)  (512 267)  (512 267)  routing T_10_16.sp4_v_b_28 <X> T_10_16.lc_trk_g2_4
 (17 11)  (513 267)  (513 267)  Enable bit of Mux _local_links/g2_mux_4 => sp4_v_b_28 lc_trk_g2_4
 (18 11)  (514 267)  (514 267)  routing T_10_16.sp4_h_l_16 <X> T_10_16.lc_trk_g2_5
 (27 11)  (523 267)  (523 267)  routing T_10_16.lc_trk_g1_0 <X> T_10_16.input0_5
 (29 11)  (525 267)  (525 267)  Enable bit of Mux _bram/lcb0_5 => lc_trk_g1_0 input0_5
 (11 12)  (507 268)  (507 268)  routing T_10_16.sp4_h_l_40 <X> T_10_16.sp4_v_b_11
 (13 12)  (509 268)  (509 268)  routing T_10_16.sp4_h_l_40 <X> T_10_16.sp4_v_b_11
 (14 12)  (510 268)  (510 268)  routing T_10_16.sp4_v_t_13 <X> T_10_16.lc_trk_g3_0
 (12 13)  (508 269)  (508 269)  routing T_10_16.sp4_h_l_40 <X> T_10_16.sp4_v_b_11
 (16 13)  (512 269)  (512 269)  routing T_10_16.sp4_v_t_13 <X> T_10_16.lc_trk_g3_0
 (17 13)  (513 269)  (513 269)  Enable bit of Mux _local_links/g3_mux_0 => sp4_v_t_13 lc_trk_g3_0
 (26 13)  (522 269)  (522 269)  routing T_10_16.lc_trk_g1_3 <X> T_10_16.input0_6
 (27 13)  (523 269)  (523 269)  routing T_10_16.lc_trk_g1_3 <X> T_10_16.input0_6
 (29 13)  (525 269)  (525 269)  Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_3 input0_6
 (0 14)  (496 270)  (496 270)  routing T_10_16.lc_trk_g2_4 <X> T_10_16.wire_bram/ram/RE
 (1 14)  (497 270)  (497 270)  Enable bit of Mux _global_links/set_rst_mux => lc_trk_g2_4 wire_bram/ram/RE
 (14 14)  (510 270)  (510 270)  routing T_10_16.sp4_v_t_25 <X> T_10_16.lc_trk_g3_4
 (22 14)  (518 270)  (518 270)  Enable bit of Mux _local_links/g3_mux_7 => sp12_v_t_12 lc_trk_g3_7
 (23 14)  (519 270)  (519 270)  routing T_10_16.sp12_v_t_12 <X> T_10_16.lc_trk_g3_7
 (26 14)  (522 270)  (522 270)  routing T_10_16.lc_trk_g0_5 <X> T_10_16.input0_7
 (1 15)  (497 271)  (497 271)  routing T_10_16.lc_trk_g2_4 <X> T_10_16.wire_bram/ram/RE
 (14 15)  (510 271)  (510 271)  routing T_10_16.sp4_v_t_25 <X> T_10_16.lc_trk_g3_4
 (16 15)  (512 271)  (512 271)  routing T_10_16.sp4_v_t_25 <X> T_10_16.lc_trk_g3_4
 (17 15)  (513 271)  (513 271)  Enable bit of Mux _local_links/g3_mux_4 => sp4_v_t_25 lc_trk_g3_4
 (29 15)  (525 271)  (525 271)  Enable bit of Mux _bram/lcb0_7 => lc_trk_g0_5 input0_7


IO_Tile_13_16

 (11 1)  (657 257)  (657 257)  routing T_13_16.span4_vert_t_12 <X> T_13_16.span4_horz_25
 (3 6)  (649 262)  (649 262)  IO control bit: IORIGHT_IE_1

 (11 7)  (657 263)  (657 263)  routing T_13_16.span4_vert_t_14 <X> T_13_16.span4_horz_37
 (3 9)  (649 265)  (649 265)  IO control bit: IORIGHT_IE_0



IO_Tile_0_15

 (3 6)  (14 246)  (14 246)  IO control bit: IOLEFT_IE_1

 (3 9)  (14 249)  (14 249)  IO control bit: IOLEFT_IE_0



RAM_Tile_3_15

 (7 1)  (133 241)  (133 241)  Ram config bit: MEMB_Power_Up_Control



LogicTile_8_15

 (9 4)  (397 244)  (397 244)  routing T_8_15.sp4_v_t_41 <X> T_8_15.sp4_h_r_4


LogicTile_9_15

 (3 4)  (445 244)  (445 244)  routing T_9_15.sp12_v_t_23 <X> T_9_15.sp12_h_r_0


RAM_Tile_10_15

 (17 0)  (513 240)  (513 240)  Enable bit of Mux _local_links/g0_mux_1 => sp4_r_v_b_25 lc_trk_g0_1
 (26 0)  (522 240)  (522 240)  routing T_10_15.lc_trk_g2_4 <X> T_10_15.input0_0
 (14 1)  (510 241)  (510 241)  routing T_10_15.sp4_h_r_0 <X> T_10_15.lc_trk_g0_0
 (15 1)  (511 241)  (511 241)  routing T_10_15.sp4_h_r_0 <X> T_10_15.lc_trk_g0_0
 (16 1)  (512 241)  (512 241)  routing T_10_15.sp4_h_r_0 <X> T_10_15.lc_trk_g0_0
 (17 1)  (513 241)  (513 241)  Enable bit of Mux _local_links/g0_mux_0 => sp4_h_r_0 lc_trk_g0_0
 (28 1)  (524 241)  (524 241)  routing T_10_15.lc_trk_g2_4 <X> T_10_15.input0_0
 (29 1)  (525 241)  (525 241)  Enable bit of Mux _bram/lcb0_0 => lc_trk_g2_4 input0_0
 (32 1)  (528 241)  (528 241)  Enable bit of Mux _bram/lcb2_0 => lc_trk_g0_0 input2_0
 (2 2)  (498 242)  (498 242)  Enable bit of Mux _global_links/clk_mux => glb_netwk_1 wire_bram/ram/WCLK
 (35 2)  (531 242)  (531 242)  routing T_10_15.lc_trk_g2_7 <X> T_10_15.input2_1
 (0 3)  (496 243)  (496 243)  routing T_10_15.glb_netwk_1 <X> T_10_15.wire_bram/ram/WCLK
 (14 3)  (510 243)  (510 243)  routing T_10_15.sp4_r_v_b_28 <X> T_10_15.lc_trk_g0_4
 (17 3)  (513 243)  (513 243)  Enable bit of Mux _local_links/g0_mux_4 => sp4_r_v_b_28 lc_trk_g0_4
 (29 3)  (525 243)  (525 243)  Enable bit of Mux _bram/lcb0_1 => lc_trk_g0_1 input0_1
 (32 3)  (528 243)  (528 243)  Enable bit of Mux _bram/lcb2_1 => lc_trk_g2_7 input2_1
 (33 3)  (529 243)  (529 243)  routing T_10_15.lc_trk_g2_7 <X> T_10_15.input2_1
 (35 3)  (531 243)  (531 243)  routing T_10_15.lc_trk_g2_7 <X> T_10_15.input2_1
 (14 4)  (510 244)  (510 244)  routing T_10_15.sp12_h_r_0 <X> T_10_15.lc_trk_g1_0
 (15 4)  (511 244)  (511 244)  routing T_10_15.sp4_h_r_1 <X> T_10_15.lc_trk_g1_1
 (16 4)  (512 244)  (512 244)  routing T_10_15.sp4_h_r_1 <X> T_10_15.lc_trk_g1_1
 (17 4)  (513 244)  (513 244)  Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1
 (21 4)  (517 244)  (517 244)  routing T_10_15.sp12_h_r_3 <X> T_10_15.lc_trk_g1_3
 (22 4)  (518 244)  (518 244)  Enable bit of Mux _local_links/g1_mux_3 => sp12_h_r_3 lc_trk_g1_3
 (24 4)  (520 244)  (520 244)  routing T_10_15.sp12_h_r_3 <X> T_10_15.lc_trk_g1_3
 (14 5)  (510 245)  (510 245)  routing T_10_15.sp12_h_r_0 <X> T_10_15.lc_trk_g1_0
 (15 5)  (511 245)  (511 245)  routing T_10_15.sp12_h_r_0 <X> T_10_15.lc_trk_g1_0
 (17 5)  (513 245)  (513 245)  Enable bit of Mux _local_links/g1_mux_0 => sp12_h_r_0 lc_trk_g1_0
 (18 5)  (514 245)  (514 245)  routing T_10_15.sp4_h_r_1 <X> T_10_15.lc_trk_g1_1
 (21 5)  (517 245)  (517 245)  routing T_10_15.sp12_h_r_3 <X> T_10_15.lc_trk_g1_3
 (28 5)  (524 245)  (524 245)  routing T_10_15.lc_trk_g2_0 <X> T_10_15.input0_2
 (29 5)  (525 245)  (525 245)  Enable bit of Mux _bram/lcb0_2 => lc_trk_g2_0 input0_2
 (32 5)  (528 245)  (528 245)  Enable bit of Mux _bram/lcb2_2 => lc_trk_g1_3 input2_2
 (34 5)  (530 245)  (530 245)  routing T_10_15.lc_trk_g1_3 <X> T_10_15.input2_2
 (35 5)  (531 245)  (531 245)  routing T_10_15.lc_trk_g1_3 <X> T_10_15.input2_2
 (15 6)  (511 246)  (511 246)  routing T_10_15.sp4_h_r_13 <X> T_10_15.lc_trk_g1_5
 (16 6)  (512 246)  (512 246)  routing T_10_15.sp4_h_r_13 <X> T_10_15.lc_trk_g1_5
 (17 6)  (513 246)  (513 246)  Enable bit of Mux _local_links/g1_mux_5 => sp4_h_r_13 lc_trk_g1_5
 (18 6)  (514 246)  (514 246)  routing T_10_15.sp4_h_r_13 <X> T_10_15.lc_trk_g1_5
 (26 6)  (522 246)  (522 246)  routing T_10_15.lc_trk_g3_4 <X> T_10_15.input0_3
 (27 6)  (523 246)  (523 246)  routing T_10_15.lc_trk_g1_1 <X> T_10_15.wire_bram/ram/WDATA_3
 (29 6)  (525 246)  (525 246)  Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_1 wire_bram/ram/WDATA_3
 (27 7)  (523 247)  (523 247)  routing T_10_15.lc_trk_g3_4 <X> T_10_15.input0_3
 (28 7)  (524 247)  (524 247)  routing T_10_15.lc_trk_g3_4 <X> T_10_15.input0_3
 (29 7)  (525 247)  (525 247)  Enable bit of Mux _bram/lcb0_3 => lc_trk_g3_4 input0_3
 (40 7)  (536 247)  (536 247)  Enable bit of Mux _out_links/OutMux4_3 => wire_bram/ram/RDATA_3 sp12_v_b_22
 (26 8)  (522 248)  (522 248)  routing T_10_15.lc_trk_g0_4 <X> T_10_15.input0_4
 (15 9)  (511 249)  (511 249)  routing T_10_15.sp4_v_b_40 <X> T_10_15.lc_trk_g2_0
 (16 9)  (512 249)  (512 249)  routing T_10_15.sp4_v_b_40 <X> T_10_15.lc_trk_g2_0
 (17 9)  (513 249)  (513 249)  Enable bit of Mux _local_links/g2_mux_0 => sp4_v_b_40 lc_trk_g2_0
 (29 9)  (525 249)  (525 249)  Enable bit of Mux _bram/lcb0_4 => lc_trk_g0_4 input0_4
 (22 10)  (518 250)  (518 250)  Enable bit of Mux _local_links/g2_mux_7 => sp4_v_t_34 lc_trk_g2_7
 (23 10)  (519 250)  (519 250)  routing T_10_15.sp4_v_t_34 <X> T_10_15.lc_trk_g2_7
 (24 10)  (520 250)  (520 250)  routing T_10_15.sp4_v_t_34 <X> T_10_15.lc_trk_g2_7
 (14 11)  (510 251)  (510 251)  routing T_10_15.sp4_h_r_28 <X> T_10_15.lc_trk_g2_4
 (15 11)  (511 251)  (511 251)  routing T_10_15.sp4_h_r_28 <X> T_10_15.lc_trk_g2_4
 (16 11)  (512 251)  (512 251)  routing T_10_15.sp4_h_r_28 <X> T_10_15.lc_trk_g2_4
 (17 11)  (513 251)  (513 251)  Enable bit of Mux _local_links/g2_mux_4 => sp4_h_r_28 lc_trk_g2_4
 (26 11)  (522 251)  (522 251)  routing T_10_15.lc_trk_g3_2 <X> T_10_15.input0_5
 (27 11)  (523 251)  (523 251)  routing T_10_15.lc_trk_g3_2 <X> T_10_15.input0_5
 (28 11)  (524 251)  (524 251)  routing T_10_15.lc_trk_g3_2 <X> T_10_15.input0_5
 (29 11)  (525 251)  (525 251)  Enable bit of Mux _bram/lcb0_5 => lc_trk_g3_2 input0_5
 (26 12)  (522 252)  (522 252)  routing T_10_15.lc_trk_g1_5 <X> T_10_15.input0_6
 (22 13)  (518 253)  (518 253)  Enable bit of Mux _local_links/g3_mux_2 => sp4_h_l_15 lc_trk_g3_2
 (23 13)  (519 253)  (519 253)  routing T_10_15.sp4_h_l_15 <X> T_10_15.lc_trk_g3_2
 (24 13)  (520 253)  (520 253)  routing T_10_15.sp4_h_l_15 <X> T_10_15.lc_trk_g3_2
 (25 13)  (521 253)  (521 253)  routing T_10_15.sp4_h_l_15 <X> T_10_15.lc_trk_g3_2
 (27 13)  (523 253)  (523 253)  routing T_10_15.lc_trk_g1_5 <X> T_10_15.input0_6
 (29 13)  (525 253)  (525 253)  Enable bit of Mux _bram/lcb0_6 => lc_trk_g1_5 input0_6
 (0 14)  (496 254)  (496 254)  routing T_10_15.lc_trk_g3_5 <X> T_10_15.wire_bram/ram/WE
 (1 14)  (497 254)  (497 254)  Enable bit of Mux _global_links/set_rst_mux => lc_trk_g3_5 wire_bram/ram/WE
 (15 14)  (511 254)  (511 254)  routing T_10_15.sp4_v_b_45 <X> T_10_15.lc_trk_g3_5
 (16 14)  (512 254)  (512 254)  routing T_10_15.sp4_v_b_45 <X> T_10_15.lc_trk_g3_5
 (17 14)  (513 254)  (513 254)  Enable bit of Mux _local_links/g3_mux_5 => sp4_v_b_45 lc_trk_g3_5
 (0 15)  (496 255)  (496 255)  routing T_10_15.lc_trk_g3_5 <X> T_10_15.wire_bram/ram/WE
 (1 15)  (497 255)  (497 255)  routing T_10_15.lc_trk_g3_5 <X> T_10_15.wire_bram/ram/WE
 (15 15)  (511 255)  (511 255)  routing T_10_15.sp4_v_b_44 <X> T_10_15.lc_trk_g3_4
 (16 15)  (512 255)  (512 255)  routing T_10_15.sp4_v_b_44 <X> T_10_15.lc_trk_g3_4
 (17 15)  (513 255)  (513 255)  Enable bit of Mux _local_links/g3_mux_4 => sp4_v_b_44 lc_trk_g3_4
 (27 15)  (523 255)  (523 255)  routing T_10_15.lc_trk_g1_0 <X> T_10_15.input0_7
 (29 15)  (525 255)  (525 255)  Enable bit of Mux _bram/lcb0_7 => lc_trk_g1_0 input0_7


LogicTile_12_15

 (12 2)  (604 242)  (604 242)  routing T_12_15.sp4_v_t_45 <X> T_12_15.sp4_h_l_39
 (11 3)  (603 243)  (603 243)  routing T_12_15.sp4_v_t_45 <X> T_12_15.sp4_h_l_39
 (13 3)  (605 243)  (605 243)  routing T_12_15.sp4_v_t_45 <X> T_12_15.sp4_h_l_39


IO_Tile_13_15

 (1 0)  (647 240)  (647 240)  Enable bit of Mux _out_links/OutMux3_0 => wire_io_cluster/io_0/D_IN_0 span4_horz_24
 (3 1)  (649 241)  (649 241)  IO control bit: IORIGHT_REN_1

 (12 1)  (658 241)  (658 241)  routing T_13_15.span4_vert_b_0 <X> T_13_15.span4_horz_25
 (17 3)  (663 243)  (663 243)  IOB_0 IO Functioning bit
 (2 6)  (648 246)  (648 246)  IO control bit: IORIGHT_REN_0

 (11 7)  (657 247)  (657 247)  routing T_13_15.span4_vert_t_14 <X> T_13_15.span4_horz_37
 (16 9)  (662 249)  (662 249)  Enable bit of Mux _out_links/OutMuxa_2 => wire_io_cluster/io_1/D_IN_0 span12_horz_4
 (17 13)  (663 253)  (663 253)  IOB_1 IO Functioning bit


IO_Tile_0_14

 (16 0)  (1 224)  (1 224)  IOB_0 IO Functioning bit
 (3 1)  (14 225)  (14 225)  IO control bit: BIOLEFT_REN_1

 (5 2)  (12 226)  (12 226)  routing T_0_14.span4_horz_27 <X> T_0_14.lc_trk_g0_3
 (6 2)  (11 226)  (11 226)  routing T_0_14.span4_horz_27 <X> T_0_14.lc_trk_g0_3
 (7 2)  (10 226)  (10 226)  Enable bit of Mux _local_links/g0_mux_3 => span4_horz_27 lc_trk_g0_3
 (5 3)  (12 227)  (12 227)  routing T_0_14.span4_horz_18 <X> T_0_14.lc_trk_g0_2
 (6 3)  (11 227)  (11 227)  routing T_0_14.span4_horz_18 <X> T_0_14.lc_trk_g0_2
 (7 3)  (10 227)  (10 227)  Enable bit of Mux _local_links/g0_mux_2 => span4_horz_18 lc_trk_g0_2
 (8 3)  (9 227)  (9 227)  routing T_0_14.span4_horz_27 <X> T_0_14.lc_trk_g0_3
 (17 3)  (0 227)  (0 227)  IOB_0 IO Functioning bit
 (16 4)  (1 228)  (1 228)  IOB_0 IO Functioning bit
 (12 5)  (5 229)  (5 229)  routing T_0_14.lc_trk_g0_2 <X> T_0_14.wire_io_cluster/io_0/D_OUT_0
 (13 5)  (4 229)  (4 229)  Enable bit of Mux _io_cluster/in_mux0_1 => lc_trk_g0_2 wire_io_cluster/io_0/D_OUT_0
 (2 6)  (15 230)  (15 230)  IO control bit: BIOLEFT_REN_0

 (3 6)  (14 230)  (14 230)  IO control bit: BIOLEFT_IE_1

 (3 9)  (14 233)  (14 233)  IO control bit: BIOLEFT_IE_0

 (16 10)  (1 234)  (1 234)  IOB_1 IO Functioning bit
 (12 11)  (5 235)  (5 235)  routing T_0_14.lc_trk_g0_3 <X> T_0_14.wire_io_cluster/io_1/D_OUT_0
 (13 11)  (4 235)  (4 235)  Enable bit of Mux _io_cluster/in_mux1_1 => lc_trk_g0_3 wire_io_cluster/io_1/D_OUT_0
 (17 13)  (0 237)  (0 237)  IOB_1 IO Functioning bit
 (16 14)  (1 238)  (1 238)  IOB_1 IO Functioning bit


LogicTile_2_14

 (4 7)  (76 231)  (76 231)  routing T_2_14.sp4_h_r_7 <X> T_2_14.sp4_h_l_38
 (6 7)  (78 231)  (78 231)  routing T_2_14.sp4_h_r_7 <X> T_2_14.sp4_h_l_38


RAM_Tile_3_14

 (5 9)  (131 233)  (131 233)  routing T_3_14.sp4_h_r_6 <X> T_3_14.sp4_v_b_6
 (9 10)  (135 234)  (135 234)  routing T_3_14.sp4_v_b_7 <X> T_3_14.sp4_h_l_42


LogicTile_6_14

 (8 10)  (284 234)  (284 234)  routing T_6_14.sp4_h_r_7 <X> T_6_14.sp4_h_l_42


LogicTile_7_14

 (5 10)  (339 234)  (339 234)  routing T_7_14.sp4_h_r_3 <X> T_7_14.sp4_h_l_43
 (4 11)  (338 235)  (338 235)  routing T_7_14.sp4_h_r_3 <X> T_7_14.sp4_h_l_43


LogicTile_9_14

 (8 0)  (450 224)  (450 224)  routing T_9_14.sp4_v_b_7 <X> T_9_14.sp4_h_r_1
 (9 0)  (451 224)  (451 224)  routing T_9_14.sp4_v_b_7 <X> T_9_14.sp4_h_r_1
 (10 0)  (452 224)  (452 224)  routing T_9_14.sp4_v_b_7 <X> T_9_14.sp4_h_r_1


RAM_Tile_10_14

 (7 0)  (503 224)  (503 224)  Ram config bit: MEMT_bram_cbit_1

 (7 1)  (503 225)  (503 225)  Ram config bit: MEMT_bram_cbit_0

 (10 1)  (506 225)  (506 225)  routing T_10_14.sp4_h_r_8 <X> T_10_14.sp4_v_b_1
 (1 2)  (497 226)  (497 226)  routing T_10_14.glb_netwk_4 <X> T_10_14.wire_bram/ram/RCLK
 (2 2)  (498 226)  (498 226)  Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_bram/ram/RCLK
 (7 2)  (503 226)  (503 226)  Ram config bit: MEMT_bram_cbit_3

 (14 2)  (510 226)  (510 226)  routing T_10_14.sp4_h_r_12 <X> T_10_14.lc_trk_g0_4
 (7 3)  (503 227)  (503 227)  Ram config bit: MEMT_bram_cbit_2

 (15 3)  (511 227)  (511 227)  routing T_10_14.sp4_h_r_12 <X> T_10_14.lc_trk_g0_4
 (16 3)  (512 227)  (512 227)  routing T_10_14.sp4_h_r_12 <X> T_10_14.lc_trk_g0_4
 (17 3)  (513 227)  (513 227)  Enable bit of Mux _local_links/g0_mux_4 => sp4_h_r_12 lc_trk_g0_4
 (7 4)  (503 228)  (503 228)  Cascade buffer Enable bit: MEMT_LC01_inmux00_bram_cbit_5

 (7 5)  (503 229)  (503 229)  Cascade bit: MEMT_LC01_inmux00_bram_cbit_4

 (7 6)  (503 230)  (503 230)  Cascade buffer Enable bit: MEMT_LC04_inmux00_bram_cbit_7

 (28 6)  (524 230)  (524 230)  routing T_10_14.lc_trk_g2_4 <X> T_10_14.wire_bram/ram/WDATA_11
 (29 6)  (525 230)  (525 230)  Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_4 wire_bram/ram/WDATA_11
 (30 6)  (526 230)  (526 230)  routing T_10_14.lc_trk_g2_4 <X> T_10_14.wire_bram/ram/WDATA_11
 (36 6)  (532 230)  (532 230)  Enable bit of Mux _out_links/OutMux8_3 => wire_bram/ram/RDATA_11 sp4_h_l_27
 (7 7)  (503 231)  (503 231)  Cascade bit: MEMT_LC04_inmux00_bram_cbit_6

 (10 7)  (506 231)  (506 231)  routing T_10_14.sp4_h_l_46 <X> T_10_14.sp4_v_t_41
 (3 8)  (499 232)  (499 232)  routing T_10_14.sp12_v_t_22 <X> T_10_14.sp12_v_b_1
 (9 10)  (505 234)  (505 234)  routing T_10_14.sp4_v_b_7 <X> T_10_14.sp4_h_l_42
 (13 10)  (509 234)  (509 234)  routing T_10_14.sp4_h_r_8 <X> T_10_14.sp4_v_t_45
 (12 11)  (508 235)  (508 235)  routing T_10_14.sp4_h_r_8 <X> T_10_14.sp4_v_t_45
 (16 11)  (512 235)  (512 235)  routing T_10_14.sp12_v_b_12 <X> T_10_14.lc_trk_g2_4
 (17 11)  (513 235)  (513 235)  Enable bit of Mux _local_links/g2_mux_4 => sp12_v_b_12 lc_trk_g2_4
 (1 14)  (497 238)  (497 238)  Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_bram/ram/RE
 (1 15)  (497 239)  (497 239)  routing T_10_14.lc_trk_g0_4 <X> T_10_14.wire_bram/ram/RE
 (8 15)  (504 239)  (504 239)  routing T_10_14.sp4_h_r_4 <X> T_10_14.sp4_v_t_47
 (9 15)  (505 239)  (505 239)  routing T_10_14.sp4_h_r_4 <X> T_10_14.sp4_v_t_47
 (10 15)  (506 239)  (506 239)  routing T_10_14.sp4_h_r_4 <X> T_10_14.sp4_v_t_47
 (13 15)  (509 239)  (509 239)  routing T_10_14.sp4_v_b_6 <X> T_10_14.sp4_h_l_46


IO_Tile_13_14

 (2 1)  (648 225)  (648 225)  Enable bit of Mux _out_links/OutMux4_0 => wire_io_cluster/io_0/D_IN_0 span4_horz_32
 (3 1)  (649 225)  (649 225)  IO control bit: IORIGHT_REN_1

 (17 3)  (663 227)  (663 227)  IOB_0 IO Functioning bit
 (2 6)  (648 230)  (648 230)  IO control bit: IORIGHT_REN_0

 (1 8)  (647 232)  (647 232)  Enable bit of Mux _out_links/OutMux3_2 => wire_io_cluster/io_1/D_IN_0 span4_horz_28
 (17 13)  (663 237)  (663 237)  IOB_1 IO Functioning bit


IO_Tile_0_13

 (16 0)  (1 208)  (1 208)  IOB_0 IO Functioning bit
 (3 1)  (14 209)  (14 209)  IO control bit: BIOLEFT_REN_1

 (5 1)  (12 209)  (12 209)  routing T_0_13.span4_horz_16 <X> T_0_13.lc_trk_g0_0
 (6 1)  (11 209)  (11 209)  routing T_0_13.span4_horz_16 <X> T_0_13.lc_trk_g0_0
 (7 1)  (10 209)  (10 209)  Enable bit of Mux _local_links/g0_mux_0 => span4_horz_16 lc_trk_g0_0
 (17 3)  (0 211)  (0 211)  IOB_0 IO Functioning bit
 (5 4)  (12 212)  (12 212)  routing T_0_13.span12_horz_5 <X> T_0_13.lc_trk_g0_5
 (7 4)  (10 212)  (10 212)  Enable bit of Mux _local_links/g0_mux_5 => span12_horz_5 lc_trk_g0_5
 (8 4)  (9 212)  (9 212)  routing T_0_13.span12_horz_5 <X> T_0_13.lc_trk_g0_5
 (16 4)  (1 212)  (1 212)  IOB_0 IO Functioning bit
 (8 5)  (9 213)  (9 213)  routing T_0_13.span12_horz_5 <X> T_0_13.lc_trk_g0_5
 (13 5)  (4 213)  (4 213)  Enable bit of Mux _io_cluster/in_mux0_1 => lc_trk_g0_0 wire_io_cluster/io_0/D_OUT_0
 (2 6)  (15 214)  (15 214)  IO control bit: BIOLEFT_REN_0

 (3 6)  (14 214)  (14 214)  IO control bit: BIOLEFT_IE_1

 (3 9)  (14 217)  (14 217)  IO control bit: BIOLEFT_IE_0

 (13 10)  (4 218)  (4 218)  routing T_0_13.lc_trk_g0_5 <X> T_0_13.wire_io_cluster/io_1/D_OUT_0
 (16 10)  (1 218)  (1 218)  IOB_1 IO Functioning bit
 (13 11)  (4 219)  (4 219)  Enable bit of Mux _io_cluster/in_mux1_1 => lc_trk_g0_5 wire_io_cluster/io_1/D_OUT_0
 (13 13)  (4 221)  (4 221)  routing T_0_13.span4_horz_19 <X> T_0_13.span4_vert_b_3
 (14 13)  (3 221)  (3 221)  routing T_0_13.span4_horz_19 <X> T_0_13.span4_vert_b_3
 (17 13)  (0 221)  (0 221)  IOB_1 IO Functioning bit
 (16 14)  (1 222)  (1 222)  IOB_1 IO Functioning bit


LogicTile_1_13



LogicTile_2_13



RAM_Tile_3_13

 (7 1)  (133 209)  (133 209)  Ram config bit: MEMB_Power_Up_Control

 (12 6)  (138 214)  (138 214)  routing T_3_13.sp4_h_r_2 <X> T_3_13.sp4_h_l_40
 (13 7)  (139 215)  (139 215)  routing T_3_13.sp4_h_r_2 <X> T_3_13.sp4_h_l_40
 (19 7)  (145 215)  (145 215)  Enable bit of Mux _span_links/cross_mux_vert_6 => sp12_v_b_13 sp4_v_t_7
 (5 10)  (131 218)  (131 218)  routing T_3_13.sp4_h_r_3 <X> T_3_13.sp4_h_l_43
 (4 11)  (130 219)  (130 219)  routing T_3_13.sp4_h_r_3 <X> T_3_13.sp4_h_l_43


LogicTile_4_13



LogicTile_5_13



LogicTile_6_13



LogicTile_7_13

 (13 3)  (347 211)  (347 211)  routing T_7_13.sp4_v_b_9 <X> T_7_13.sp4_h_l_39
 (6 7)  (340 215)  (340 215)  routing T_7_13.sp4_h_r_3 <X> T_7_13.sp4_h_l_38


LogicTile_8_13



LogicTile_9_13



RAM_Tile_10_13

 (2 1)  (498 209)  (498 209)  Column buffer control bit: MEMB_colbuf_cntl_1

 (2 2)  (498 210)  (498 210)  Enable bit of Mux _global_links/clk_mux => glb_netwk_1 wire_bram/ram/WCLK
 (14 2)  (510 210)  (510 210)  routing T_10_13.sp4_v_b_12 <X> T_10_13.lc_trk_g0_4
 (0 3)  (496 211)  (496 211)  routing T_10_13.glb_netwk_1 <X> T_10_13.wire_bram/ram/WCLK
 (14 3)  (510 211)  (510 211)  routing T_10_13.sp4_v_b_12 <X> T_10_13.lc_trk_g0_4
 (16 3)  (512 211)  (512 211)  routing T_10_13.sp4_v_b_12 <X> T_10_13.lc_trk_g0_4
 (17 3)  (513 211)  (513 211)  Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_12 lc_trk_g0_4
 (17 6)  (513 214)  (513 214)  Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_5 lc_trk_g1_5
 (27 6)  (523 214)  (523 214)  routing T_10_13.lc_trk_g1_5 <X> T_10_13.wire_bram/ram/WDATA_3
 (29 6)  (525 214)  (525 214)  Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_5 wire_bram/ram/WDATA_3
 (30 6)  (526 214)  (526 214)  routing T_10_13.lc_trk_g1_5 <X> T_10_13.wire_bram/ram/WDATA_3
 (36 6)  (532 214)  (532 214)  Enable bit of Mux _out_links/OutMux8_3 => wire_bram/ram/RDATA_3 sp4_h_l_27
 (19 7)  (515 215)  (515 215)  Enable bit of Mux _span_links/cross_mux_vert_6 => sp12_v_b_13 sp4_v_t_7
 (2 9)  (498 217)  (498 217)  Column buffer control bit: MEMB_colbuf_cntl_4

 (3 11)  (499 219)  (499 219)  routing T_10_13.sp12_v_b_1 <X> T_10_13.sp12_h_l_22
 (1 14)  (497 222)  (497 222)  Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_bram/ram/WE
 (1 15)  (497 223)  (497 223)  routing T_10_13.lc_trk_g0_4 <X> T_10_13.wire_bram/ram/WE


LogicTile_11_13



LogicTile_12_13



IO_Tile_13_13

 (3 6)  (649 214)  (649 214)  IO control bit: IORIGHT_IE_1

 (3 9)  (649 217)  (649 217)  IO control bit: IORIGHT_IE_0



IO_Tile_0_12

 (16 0)  (1 192)  (1 192)  IOB_0 IO Functioning bit
 (3 1)  (14 193)  (14 193)  IO control bit: BIOLEFT_REN_1

 (17 3)  (0 195)  (0 195)  IOB_0 IO Functioning bit
 (12 4)  (5 196)  (5 196)  routing T_0_12.lc_trk_g1_7 <X> T_0_12.wire_io_cluster/io_0/D_OUT_0
 (13 4)  (4 196)  (4 196)  routing T_0_12.lc_trk_g1_7 <X> T_0_12.wire_io_cluster/io_0/D_OUT_0
 (16 4)  (1 196)  (1 196)  IOB_0 IO Functioning bit
 (12 5)  (5 197)  (5 197)  routing T_0_12.lc_trk_g1_7 <X> T_0_12.wire_io_cluster/io_0/D_OUT_0
 (13 5)  (4 197)  (4 197)  Enable bit of Mux _io_cluster/in_mux0_1 => lc_trk_g1_7 wire_io_cluster/io_0/D_OUT_0
 (2 6)  (15 198)  (15 198)  IO control bit: BIOLEFT_REN_0

 (3 6)  (14 198)  (14 198)  IO control bit: BIOLEFT_IE_1

 (3 9)  (14 201)  (14 201)  IO control bit: BIOLEFT_IE_0

 (12 10)  (5 202)  (5 202)  routing T_0_12.lc_trk_g1_2 <X> T_0_12.wire_io_cluster/io_1/D_OUT_0
 (16 10)  (1 202)  (1 202)  IOB_1 IO Functioning bit
 (4 11)  (13 203)  (13 203)  routing T_0_12.span12_horz_18 <X> T_0_12.lc_trk_g1_2
 (6 11)  (11 203)  (11 203)  routing T_0_12.span12_horz_18 <X> T_0_12.lc_trk_g1_2
 (7 11)  (10 203)  (10 203)  Enable bit of Mux _local_links/g1_mux_2 => span12_horz_18 lc_trk_g1_2
 (12 11)  (5 203)  (5 203)  routing T_0_12.lc_trk_g1_2 <X> T_0_12.wire_io_cluster/io_1/D_OUT_0
 (13 11)  (4 203)  (4 203)  Enable bit of Mux _io_cluster/in_mux1_1 => lc_trk_g1_2 wire_io_cluster/io_1/D_OUT_0
 (17 13)  (0 205)  (0 205)  IOB_1 IO Functioning bit
 (5 14)  (12 206)  (12 206)  routing T_0_12.span4_vert_b_15 <X> T_0_12.lc_trk_g1_7
 (7 14)  (10 206)  (10 206)  Enable bit of Mux _local_links/g1_mux_7 => span4_vert_b_15 lc_trk_g1_7
 (8 14)  (9 206)  (9 206)  routing T_0_12.span4_vert_b_15 <X> T_0_12.lc_trk_g1_7
 (16 14)  (1 206)  (1 206)  IOB_1 IO Functioning bit


LogicTile_1_12



LogicTile_2_12



RAM_Tile_3_12

 (3 10)  (129 202)  (129 202)  routing T_3_12.sp12_h_r_1 <X> T_3_12.sp12_h_l_22
 (3 11)  (129 203)  (129 203)  routing T_3_12.sp12_h_r_1 <X> T_3_12.sp12_h_l_22


LogicTile_4_12



LogicTile_5_12



LogicTile_6_12



LogicTile_7_12



LogicTile_8_12



LogicTile_9_12



RAM_Tile_10_12

 (7 0)  (503 192)  (503 192)  Ram config bit: MEMT_bram_cbit_1

 (7 1)  (503 193)  (503 193)  Ram config bit: MEMT_bram_cbit_0

 (1 2)  (497 194)  (497 194)  routing T_10_12.glb_netwk_4 <X> T_10_12.wire_bram/ram/RCLK
 (2 2)  (498 194)  (498 194)  Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_bram/ram/RCLK
 (7 2)  (503 194)  (503 194)  Ram config bit: MEMT_bram_cbit_3

 (7 3)  (503 195)  (503 195)  Ram config bit: MEMT_bram_cbit_2

 (7 4)  (503 196)  (503 196)  Cascade buffer Enable bit: MEMT_LC01_inmux00_bram_cbit_5

 (7 5)  (503 197)  (503 197)  Cascade bit: MEMT_LC01_inmux00_bram_cbit_4

 (7 6)  (503 198)  (503 198)  Cascade buffer Enable bit: MEMT_LC04_inmux00_bram_cbit_7

 (17 6)  (513 198)  (513 198)  Enable bit of Mux _local_links/g1_mux_5 => sp4_r_v_b_5 lc_trk_g1_5
 (27 6)  (523 198)  (523 198)  routing T_10_12.lc_trk_g1_5 <X> T_10_12.wire_bram/ram/WDATA_11
 (29 6)  (525 198)  (525 198)  Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_5 wire_bram/ram/WDATA_11
 (30 6)  (526 198)  (526 198)  routing T_10_12.lc_trk_g1_5 <X> T_10_12.wire_bram/ram/WDATA_11
 (37 6)  (533 198)  (533 198)  Enable bit of Mux _out_links/OutMux5_3 => wire_bram/ram/RDATA_11 sp12_h_l_13
 (7 7)  (503 199)  (503 199)  Cascade bit: MEMT_LC04_inmux00_bram_cbit_6

 (0 14)  (496 206)  (496 206)  routing T_10_12.lc_trk_g3_5 <X> T_10_12.wire_bram/ram/RE
 (1 14)  (497 206)  (497 206)  Enable bit of Mux _global_links/set_rst_mux => lc_trk_g3_5 wire_bram/ram/RE
 (17 14)  (513 206)  (513 206)  Enable bit of Mux _local_links/g3_mux_5 => bnl_op_5 lc_trk_g3_5
 (18 14)  (514 206)  (514 206)  routing T_10_12.bnl_op_5 <X> T_10_12.lc_trk_g3_5
 (0 15)  (496 207)  (496 207)  routing T_10_12.lc_trk_g3_5 <X> T_10_12.wire_bram/ram/RE
 (1 15)  (497 207)  (497 207)  routing T_10_12.lc_trk_g3_5 <X> T_10_12.wire_bram/ram/RE
 (18 15)  (514 207)  (514 207)  routing T_10_12.bnl_op_5 <X> T_10_12.lc_trk_g3_5


LogicTile_11_12



LogicTile_12_12



IO_Tile_13_12

 (2 3)  (648 195)  (648 195)  Enable bit of Mux _out_links/OutMux9_0 => wire_io_cluster/io_0/D_IN_0 span4_vert_b_12
 (17 3)  (663 195)  (663 195)  IOB_0 IO Functioning bit


IO_Tile_0_11

 (3 6)  (14 182)  (14 182)  IO control bit: BIOLEFT_IE_1

 (3 9)  (14 185)  (14 185)  IO control bit: BIOLEFT_IE_0

 (11 12)  (6 188)  (6 188)  routing T_0_11.span4_horz_19 <X> T_0_11.span4_vert_t_15
 (12 12)  (5 188)  (5 188)  routing T_0_11.span4_horz_19 <X> T_0_11.span4_vert_t_15


RAM_Tile_3_11

 (7 1)  (133 177)  (133 177)  Ram config bit: MEMB_Power_Up_Control

 (6 11)  (132 187)  (132 187)  routing T_3_11.sp4_h_r_6 <X> T_3_11.sp4_h_l_43


LogicTile_7_11

 (5 10)  (339 186)  (339 186)  routing T_7_11.sp4_h_r_3 <X> T_7_11.sp4_h_l_43
 (4 11)  (338 187)  (338 187)  routing T_7_11.sp4_h_r_3 <X> T_7_11.sp4_h_l_43


LogicTile_9_11

 (36 10)  (478 186)  (478 186)  LC_5 Logic Functioning bit
 (37 10)  (479 186)  (479 186)  LC_5 Logic Functioning bit
 (38 10)  (480 186)  (480 186)  LC_5 Logic Functioning bit
 (39 10)  (481 186)  (481 186)  LC_5 Logic Functioning bit
 (40 10)  (482 186)  (482 186)  LC_5 Logic Functioning bit
 (41 10)  (483 186)  (483 186)  LC_5 Logic Functioning bit
 (42 10)  (484 186)  (484 186)  LC_5 Logic Functioning bit
 (43 10)  (485 186)  (485 186)  LC_5 Logic Functioning bit
 (46 10)  (488 186)  (488 186)  Enable bit of Mux _out_links/OutMux7_5 => wire_logic_cluster/lc_5/out sp4_h_l_15
 (51 10)  (493 186)  (493 186)  Enable bit of Mux _out_links/OutMux2_5 => wire_logic_cluster/lc_5/out sp4_v_b_42
 (36 11)  (478 187)  (478 187)  LC_5 Logic Functioning bit
 (37 11)  (479 187)  (479 187)  LC_5 Logic Functioning bit
 (38 11)  (480 187)  (480 187)  LC_5 Logic Functioning bit
 (39 11)  (481 187)  (481 187)  LC_5 Logic Functioning bit
 (40 11)  (482 187)  (482 187)  LC_5 Logic Functioning bit
 (41 11)  (483 187)  (483 187)  LC_5 Logic Functioning bit
 (42 11)  (484 187)  (484 187)  LC_5 Logic Functioning bit
 (43 11)  (485 187)  (485 187)  LC_5 Logic Functioning bit
 (53 11)  (495 187)  (495 187)  Enable bit of Mux _out_links/OutMuxb_5 => wire_logic_cluster/lc_5/out sp4_r_v_b_43


RAM_Tile_10_11

 (2 1)  (498 177)  (498 177)  Column buffer control bit: MEMB_colbuf_cntl_1

 (2 2)  (498 178)  (498 178)  Enable bit of Mux _global_links/clk_mux => glb_netwk_1 wire_bram/ram/WCLK
 (0 3)  (496 179)  (496 179)  routing T_10_11.glb_netwk_1 <X> T_10_11.wire_bram/ram/WCLK
 (3 6)  (499 182)  (499 182)  routing T_10_11.sp12_h_r_0 <X> T_10_11.sp12_v_t_23
 (22 6)  (518 182)  (518 182)  Enable bit of Mux _local_links/g1_mux_7 => sp12_h_l_20 lc_trk_g1_7
 (23 6)  (519 182)  (519 182)  routing T_10_11.sp12_h_l_20 <X> T_10_11.lc_trk_g1_7
 (27 6)  (523 182)  (523 182)  routing T_10_11.lc_trk_g1_7 <X> T_10_11.wire_bram/ram/WDATA_3
 (29 6)  (525 182)  (525 182)  Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_7 wire_bram/ram/WDATA_3
 (30 6)  (526 182)  (526 182)  routing T_10_11.lc_trk_g1_7 <X> T_10_11.wire_bram/ram/WDATA_3
 (36 6)  (532 182)  (532 182)  Enable bit of Mux _out_links/OutMux8_3 => wire_bram/ram/RDATA_3 sp4_h_l_27
 (3 7)  (499 183)  (499 183)  routing T_10_11.sp12_h_r_0 <X> T_10_11.sp12_v_t_23
 (21 7)  (517 183)  (517 183)  routing T_10_11.sp12_h_l_20 <X> T_10_11.lc_trk_g1_7
 (30 7)  (526 183)  (526 183)  routing T_10_11.lc_trk_g1_7 <X> T_10_11.wire_bram/ram/WDATA_3
 (2 9)  (498 185)  (498 185)  Column buffer control bit: MEMB_colbuf_cntl_4

 (14 10)  (510 186)  (510 186)  routing T_10_11.sp4_v_t_25 <X> T_10_11.lc_trk_g2_4
 (14 11)  (510 187)  (510 187)  routing T_10_11.sp4_v_t_25 <X> T_10_11.lc_trk_g2_4
 (16 11)  (512 187)  (512 187)  routing T_10_11.sp4_v_t_25 <X> T_10_11.lc_trk_g2_4
 (17 11)  (513 187)  (513 187)  Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_25 lc_trk_g2_4
 (0 14)  (496 190)  (496 190)  routing T_10_11.lc_trk_g2_4 <X> T_10_11.wire_bram/ram/WE
 (1 14)  (497 190)  (497 190)  Enable bit of Mux _global_links/set_rst_mux => lc_trk_g2_4 wire_bram/ram/WE
 (1 15)  (497 191)  (497 191)  routing T_10_11.lc_trk_g2_4 <X> T_10_11.wire_bram/ram/WE


LogicTile_11_11

 (3 3)  (541 179)  (541 179)  routing T_11_11.sp12_v_b_0 <X> T_11_11.sp12_h_l_23
 (11 8)  (549 184)  (549 184)  routing T_11_11.sp4_h_l_39 <X> T_11_11.sp4_v_b_8
 (13 8)  (551 184)  (551 184)  routing T_11_11.sp4_h_l_39 <X> T_11_11.sp4_v_b_8
 (12 9)  (550 185)  (550 185)  routing T_11_11.sp4_h_l_39 <X> T_11_11.sp4_v_b_8


IO_Tile_13_11

 (2 6)  (648 182)  (648 182)  IO control bit: IORIGHT_REN_0

 (3 6)  (649 182)  (649 182)  IO control bit: IORIGHT_IE_1

 (16 9)  (662 185)  (662 185)  Enable bit of Mux _out_links/OutMuxa_2 => wire_io_cluster/io_1/D_IN_0 span12_horz_4
 (17 13)  (663 189)  (663 189)  IOB_1 IO Functioning bit


IO_Tile_0_10

 (16 0)  (1 160)  (1 160)  IOB_0 IO Functioning bit
 (3 1)  (14 161)  (14 161)  IO control bit: BIOLEFT_REN_1

 (5 2)  (12 162)  (12 162)  routing T_0_10.span4_horz_19 <X> T_0_10.lc_trk_g0_3
 (6 2)  (11 162)  (11 162)  routing T_0_10.span4_horz_19 <X> T_0_10.lc_trk_g0_3
 (7 2)  (10 162)  (10 162)  Enable bit of Mux _local_links/g0_mux_3 => span4_horz_19 lc_trk_g0_3
 (17 3)  (0 163)  (0 163)  IOB_0 IO Functioning bit
 (12 4)  (5 164)  (5 164)  routing T_0_10.lc_trk_g1_7 <X> T_0_10.wire_io_cluster/io_0/D_OUT_0
 (13 4)  (4 164)  (4 164)  routing T_0_10.lc_trk_g1_7 <X> T_0_10.wire_io_cluster/io_0/D_OUT_0
 (16 4)  (1 164)  (1 164)  IOB_0 IO Functioning bit
 (12 5)  (5 165)  (5 165)  routing T_0_10.lc_trk_g1_7 <X> T_0_10.wire_io_cluster/io_0/D_OUT_0
 (13 5)  (4 165)  (4 165)  Enable bit of Mux _io_cluster/in_mux0_1 => lc_trk_g1_7 wire_io_cluster/io_0/D_OUT_0
 (2 6)  (15 166)  (15 166)  IO control bit: BIOLEFT_REN_0

 (3 6)  (14 166)  (14 166)  IO control bit: BIOLEFT_IE_1

 (3 9)  (14 169)  (14 169)  IO control bit: BIOLEFT_IE_0

 (16 10)  (1 170)  (1 170)  IOB_1 IO Functioning bit
 (12 11)  (5 171)  (5 171)  routing T_0_10.lc_trk_g0_3 <X> T_0_10.wire_io_cluster/io_1/D_OUT_0
 (13 11)  (4 171)  (4 171)  Enable bit of Mux _io_cluster/in_mux1_1 => lc_trk_g0_3 wire_io_cluster/io_1/D_OUT_0
 (17 13)  (0 173)  (0 173)  IOB_1 IO Functioning bit
 (5 14)  (12 174)  (12 174)  routing T_0_10.span4_vert_b_15 <X> T_0_10.lc_trk_g1_7
 (7 14)  (10 174)  (10 174)  Enable bit of Mux _local_links/g1_mux_7 => span4_vert_b_15 lc_trk_g1_7
 (8 14)  (9 174)  (9 174)  routing T_0_10.span4_vert_b_15 <X> T_0_10.lc_trk_g1_7
 (16 14)  (1 174)  (1 174)  IOB_1 IO Functioning bit


RAM_Tile_3_10

 (5 10)  (131 170)  (131 170)  routing T_3_10.sp4_v_t_43 <X> T_3_10.sp4_h_l_43
 (6 11)  (132 171)  (132 171)  routing T_3_10.sp4_v_t_43 <X> T_3_10.sp4_h_l_43


LogicTile_9_10

 (12 8)  (454 168)  (454 168)  routing T_9_10.sp4_v_b_8 <X> T_9_10.sp4_h_r_8
 (11 9)  (453 169)  (453 169)  routing T_9_10.sp4_v_b_8 <X> T_9_10.sp4_h_r_8


RAM_Tile_10_10

 (7 0)  (503 160)  (503 160)  Ram config bit: MEMT_bram_cbit_1

 (7 1)  (503 161)  (503 161)  Ram config bit: MEMT_bram_cbit_0

 (9 1)  (505 161)  (505 161)  routing T_10_10.sp4_v_t_36 <X> T_10_10.sp4_v_b_1
 (1 2)  (497 162)  (497 162)  routing T_10_10.glb_netwk_4 <X> T_10_10.wire_bram/ram/RCLK
 (2 2)  (498 162)  (498 162)  Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_bram/ram/RCLK
 (7 2)  (503 162)  (503 162)  Ram config bit: MEMT_bram_cbit_3

 (7 3)  (503 163)  (503 163)  Ram config bit: MEMT_bram_cbit_2

 (7 4)  (503 164)  (503 164)  Cascade buffer Enable bit: MEMT_LC01_inmux00_bram_cbit_5

 (7 5)  (503 165)  (503 165)  Cascade bit: MEMT_LC01_inmux00_bram_cbit_4

 (7 6)  (503 166)  (503 166)  Cascade buffer Enable bit: MEMT_LC04_inmux00_bram_cbit_7

 (15 6)  (511 166)  (511 166)  routing T_10_10.sp4_h_l_8 <X> T_10_10.lc_trk_g1_5
 (16 6)  (512 166)  (512 166)  routing T_10_10.sp4_h_l_8 <X> T_10_10.lc_trk_g1_5
 (17 6)  (513 166)  (513 166)  Enable bit of Mux _local_links/g1_mux_5 => sp4_h_l_8 lc_trk_g1_5
 (18 6)  (514 166)  (514 166)  routing T_10_10.sp4_h_l_8 <X> T_10_10.lc_trk_g1_5
 (27 6)  (523 166)  (523 166)  routing T_10_10.lc_trk_g1_5 <X> T_10_10.wire_bram/ram/WDATA_11
 (29 6)  (525 166)  (525 166)  Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_5 wire_bram/ram/WDATA_11
 (30 6)  (526 166)  (526 166)  routing T_10_10.lc_trk_g1_5 <X> T_10_10.wire_bram/ram/WDATA_11
 (39 6)  (535 166)  (535 166)  Enable bit of Mux _out_links/OutMux3_3 => wire_bram/ram/RDATA_11 sp12_v_b_6
 (7 7)  (503 167)  (503 167)  Cascade bit: MEMT_LC04_inmux00_bram_cbit_6

 (18 7)  (514 167)  (514 167)  routing T_10_10.sp4_h_l_8 <X> T_10_10.lc_trk_g1_5
 (0 14)  (496 174)  (496 174)  routing T_10_10.lc_trk_g3_5 <X> T_10_10.wire_bram/ram/RE
 (1 14)  (497 174)  (497 174)  Enable bit of Mux _global_links/set_rst_mux => lc_trk_g3_5 wire_bram/ram/RE
 (15 14)  (511 174)  (511 174)  routing T_10_10.tnl_op_5 <X> T_10_10.lc_trk_g3_5
 (17 14)  (513 174)  (513 174)  Enable bit of Mux _local_links/g3_mux_5 => tnl_op_5 lc_trk_g3_5
 (0 15)  (496 175)  (496 175)  routing T_10_10.lc_trk_g3_5 <X> T_10_10.wire_bram/ram/RE
 (1 15)  (497 175)  (497 175)  routing T_10_10.lc_trk_g3_5 <X> T_10_10.wire_bram/ram/RE
 (18 15)  (514 175)  (514 175)  routing T_10_10.tnl_op_5 <X> T_10_10.lc_trk_g3_5


IO_Tile_13_10

 (3 1)  (649 161)  (649 161)  IO control bit: BIORIGHT_REN_1

 (3 9)  (649 169)  (649 169)  IO control bit: BIORIGHT_IE_0



IO_Tile_0_9

 (3 1)  (14 145)  (14 145)  IO control bit: GIOLEFT0_REN_1

 (17 3)  (0 147)  (0 147)  IOB_0 IO Functioning bit
 (2 6)  (15 150)  (15 150)  IO control bit: GIOLEFT0_REN_0

 (3 9)  (14 153)  (14 153)  IO control bit: GIOLEFT0_IE_0

 (12 10)  (5 154)  (5 154)  routing T_0_9.lc_trk_g1_2 <X> T_0_9.wire_io_cluster/io_1/D_OUT_0
 (16 10)  (1 154)  (1 154)  IOB_1 IO Functioning bit
 (5 11)  (12 155)  (12 155)  routing T_0_9.span4_horz_18 <X> T_0_9.lc_trk_g1_2
 (6 11)  (11 155)  (11 155)  routing T_0_9.span4_horz_18 <X> T_0_9.lc_trk_g1_2
 (7 11)  (10 155)  (10 155)  Enable bit of Mux _local_links/g1_mux_2 => span4_horz_18 lc_trk_g1_2
 (12 11)  (5 155)  (5 155)  routing T_0_9.lc_trk_g1_2 <X> T_0_9.wire_io_cluster/io_1/D_OUT_0
 (13 11)  (4 155)  (4 155)  Enable bit of Mux _io_cluster/in_mux1_1 => lc_trk_g1_2 wire_io_cluster/io_1/D_OUT_0
 (17 13)  (0 157)  (0 157)  IOB_1 IO Functioning bit
 (16 14)  (1 158)  (1 158)  IOB_1 IO Functioning bit


RAM_Tile_3_9

 (7 1)  (133 145)  (133 145)  Ram config bit: MEMB_Power_Up_Control

 (9 10)  (135 154)  (135 154)  routing T_3_9.sp4_v_b_7 <X> T_3_9.sp4_h_l_42


LogicTile_7_9

 (4 14)  (338 158)  (338 158)  routing T_7_9.sp4_h_r_3 <X> T_7_9.sp4_v_t_44
 (6 14)  (340 158)  (340 158)  routing T_7_9.sp4_h_r_3 <X> T_7_9.sp4_v_t_44
 (5 15)  (339 159)  (339 159)  routing T_7_9.sp4_h_r_3 <X> T_7_9.sp4_v_t_44


RAM_Tile_10_9

 (2 2)  (498 146)  (498 146)  Enable bit of Mux _global_links/clk_mux => glb_netwk_1 wire_bram/ram/WCLK
 (14 2)  (510 146)  (510 146)  routing T_10_9.sp4_v_b_12 <X> T_10_9.lc_trk_g0_4
 (0 3)  (496 147)  (496 147)  routing T_10_9.glb_netwk_1 <X> T_10_9.wire_bram/ram/WCLK
 (14 3)  (510 147)  (510 147)  routing T_10_9.sp4_v_b_12 <X> T_10_9.lc_trk_g0_4
 (16 3)  (512 147)  (512 147)  routing T_10_9.sp4_v_b_12 <X> T_10_9.lc_trk_g0_4
 (17 3)  (513 147)  (513 147)  Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_12 lc_trk_g0_4
 (28 6)  (524 150)  (524 150)  routing T_10_9.lc_trk_g2_0 <X> T_10_9.wire_bram/ram/WDATA_3
 (29 6)  (525 150)  (525 150)  Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_0 wire_bram/ram/WDATA_3
 (36 6)  (532 150)  (532 150)  Enable bit of Mux _out_links/OutMux8_3 => wire_bram/ram/RDATA_3 sp4_h_l_27
 (14 8)  (510 152)  (510 152)  routing T_10_9.sp12_v_b_0 <X> T_10_9.lc_trk_g2_0
 (14 9)  (510 153)  (510 153)  routing T_10_9.sp12_v_b_0 <X> T_10_9.lc_trk_g2_0
 (15 9)  (511 153)  (511 153)  routing T_10_9.sp12_v_b_0 <X> T_10_9.lc_trk_g2_0
 (17 9)  (513 153)  (513 153)  Enable bit of Mux _local_links/g2_mux_0 => sp12_v_b_0 lc_trk_g2_0
 (1 14)  (497 158)  (497 158)  Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_bram/ram/WE
 (1 15)  (497 159)  (497 159)  routing T_10_9.lc_trk_g0_4 <X> T_10_9.wire_bram/ram/WE


LogicTile_11_9

 (13 6)  (551 150)  (551 150)  routing T_11_9.sp4_h_r_5 <X> T_11_9.sp4_v_t_40
 (12 7)  (550 151)  (550 151)  routing T_11_9.sp4_h_r_5 <X> T_11_9.sp4_v_t_40


IO_Tile_13_9

 (0 0)  (646 144)  (646 144)  Enable bit of Mux _out_links/OutMux2_0 => wire_io_cluster/io_0/D_IN_0 span4_horz_16
 (17 3)  (663 147)  (663 147)  IOB_0 IO Functioning bit
 (2 6)  (648 150)  (648 150)  IO control bit: GIORIGHT0_REN_0

 (3 6)  (649 150)  (649 150)  IO control bit: GIORIGHT0_IE_1



IO_Tile_0_8

 (16 0)  (1 128)  (1 128)  IOB_0 IO Functioning bit
 (3 1)  (14 129)  (14 129)  IO control bit: GIOLEFT1_REN_1

 (5 3)  (12 131)  (12 131)  routing T_0_8.span4_horz_18 <X> T_0_8.lc_trk_g0_2
 (6 3)  (11 131)  (11 131)  routing T_0_8.span4_horz_18 <X> T_0_8.lc_trk_g0_2
 (7 3)  (10 131)  (10 131)  Enable bit of Mux _local_links/g0_mux_2 => span4_horz_18 lc_trk_g0_2
 (17 3)  (0 131)  (0 131)  IOB_0 IO Functioning bit
 (16 4)  (1 132)  (1 132)  IOB_0 IO Functioning bit
 (12 5)  (5 133)  (5 133)  routing T_0_8.lc_trk_g0_2 <X> T_0_8.wire_io_cluster/io_0/D_OUT_0
 (13 5)  (4 133)  (4 133)  Enable bit of Mux _io_cluster/in_mux0_1 => lc_trk_g0_2 wire_io_cluster/io_0/D_OUT_0
 (2 6)  (15 134)  (15 134)  IO control bit: GIOLEFT1_REN_0

 (3 6)  (14 134)  (14 134)  IO control bit: GIOLEFT1_IE_1

 (17 13)  (0 141)  (0 141)  IOB_1 IO Functioning bit


RAM_Tile_3_8

 (19 7)  (145 135)  (145 135)  Enable bit of Mux _span_links/cross_mux_vert_6 => sp12_v_t_10 sp4_v_t_7
 (9 10)  (135 138)  (135 138)  routing T_3_8.sp4_v_b_7 <X> T_3_8.sp4_h_l_42


LogicTile_7_8

 (8 8)  (342 136)  (342 136)  routing T_7_8.sp4_v_b_1 <X> T_7_8.sp4_h_r_7
 (9 8)  (343 136)  (343 136)  routing T_7_8.sp4_v_b_1 <X> T_7_8.sp4_h_r_7
 (10 8)  (344 136)  (344 136)  routing T_7_8.sp4_v_b_1 <X> T_7_8.sp4_h_r_7


RAM_Tile_10_8

 (7 0)  (503 128)  (503 128)  Ram config bit: MEMT_bram_cbit_1

 (7 1)  (503 129)  (503 129)  Ram config bit: MEMT_bram_cbit_0

 (1 2)  (497 130)  (497 130)  routing T_10_8.glb_netwk_4 <X> T_10_8.wire_bram/ram/RCLK
 (2 2)  (498 130)  (498 130)  Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_bram/ram/RCLK
 (7 2)  (503 130)  (503 130)  Ram config bit: MEMT_bram_cbit_3

 (7 3)  (503 131)  (503 131)  Ram config bit: MEMT_bram_cbit_2

 (7 4)  (503 132)  (503 132)  Cascade buffer Enable bit: MEMT_LC01_inmux00_bram_cbit_5

 (7 5)  (503 133)  (503 133)  Cascade bit: MEMT_LC01_inmux00_bram_cbit_4

 (3 6)  (499 134)  (499 134)  routing T_10_8.sp12_h_r_0 <X> T_10_8.sp12_v_t_23
 (7 6)  (503 134)  (503 134)  Cascade buffer Enable bit: MEMT_LC04_inmux00_bram_cbit_7

 (28 6)  (524 134)  (524 134)  routing T_10_8.lc_trk_g2_2 <X> T_10_8.wire_bram/ram/WDATA_11
 (29 6)  (525 134)  (525 134)  Enable bit of Mux _bram/lcb1_3 => lc_trk_g2_2 wire_bram/ram/WDATA_11
 (3 7)  (499 135)  (499 135)  routing T_10_8.sp12_h_r_0 <X> T_10_8.sp12_v_t_23
 (7 7)  (503 135)  (503 135)  Cascade bit: MEMT_LC04_inmux00_bram_cbit_6

 (30 7)  (526 135)  (526 135)  routing T_10_8.lc_trk_g2_2 <X> T_10_8.wire_bram/ram/WDATA_11
 (40 7)  (536 135)  (536 135)  Enable bit of Mux _out_links/OutMux4_3 => wire_bram/ram/RDATA_11 sp12_v_t_21
 (25 8)  (521 136)  (521 136)  routing T_10_8.sp4_h_r_42 <X> T_10_8.lc_trk_g2_2
 (22 9)  (518 137)  (518 137)  Enable bit of Mux _local_links/g2_mux_2 => sp4_h_r_42 lc_trk_g2_2
 (23 9)  (519 137)  (519 137)  routing T_10_8.sp4_h_r_42 <X> T_10_8.lc_trk_g2_2
 (24 9)  (520 137)  (520 137)  routing T_10_8.sp4_h_r_42 <X> T_10_8.lc_trk_g2_2
 (25 9)  (521 137)  (521 137)  routing T_10_8.sp4_h_r_42 <X> T_10_8.lc_trk_g2_2
 (0 14)  (496 142)  (496 142)  routing T_10_8.lc_trk_g3_5 <X> T_10_8.wire_bram/ram/RE
 (1 14)  (497 142)  (497 142)  Enable bit of Mux _global_links/set_rst_mux => lc_trk_g3_5 wire_bram/ram/RE
 (17 14)  (513 142)  (513 142)  Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_45 lc_trk_g3_5
 (0 15)  (496 143)  (496 143)  routing T_10_8.lc_trk_g3_5 <X> T_10_8.wire_bram/ram/RE
 (1 15)  (497 143)  (497 143)  routing T_10_8.lc_trk_g3_5 <X> T_10_8.wire_bram/ram/RE
 (18 15)  (514 143)  (514 143)  routing T_10_8.sp4_r_v_b_45 <X> T_10_8.lc_trk_g3_5


LogicTile_11_8

 (13 6)  (551 134)  (551 134)  routing T_11_8.sp4_v_b_5 <X> T_11_8.sp4_v_t_40


IO_Tile_13_8

 (3 1)  (649 129)  (649 129)  IO control bit: GIORIGHT1_REN_1

 (3 9)  (649 137)  (649 137)  IO control bit: GIORIGHT1_IE_0

 (16 9)  (662 137)  (662 137)  Enable bit of Mux _out_links/OutMuxa_2 => wire_io_cluster/io_1/D_IN_0 span12_horz_4
 (17 13)  (663 141)  (663 141)  IOB_1 IO Functioning bit


IO_Tile_0_7

 (3 6)  (14 118)  (14 118)  IO control bit: BIOLEFT_IE_1

 (3 9)  (14 121)  (14 121)  IO control bit: BIOLEFT_IE_0



RAM_Tile_3_7

 (7 1)  (133 113)  (133 113)  Ram config bit: MEMB_Power_Up_Control

 (19 7)  (145 119)  (145 119)  Enable bit of Mux _span_links/cross_mux_vert_6 => sp12_v_b_13 sp4_v_t_7
 (3 14)  (129 126)  (129 126)  routing T_3_7.sp12_h_r_1 <X> T_3_7.sp12_v_t_22
 (3 15)  (129 127)  (129 127)  routing T_3_7.sp12_h_r_1 <X> T_3_7.sp12_v_t_22


LogicTile_7_7

 (3 4)  (337 116)  (337 116)  routing T_7_7.sp12_v_b_0 <X> T_7_7.sp12_h_r_0
 (3 5)  (337 117)  (337 117)  routing T_7_7.sp12_v_b_0 <X> T_7_7.sp12_h_r_0


RAM_Tile_10_7

 (2 2)  (498 114)  (498 114)  Enable bit of Mux _global_links/clk_mux => glb_netwk_1 wire_bram/ram/WCLK
 (0 3)  (496 115)  (496 115)  routing T_10_7.glb_netwk_1 <X> T_10_7.wire_bram/ram/WCLK
 (21 6)  (517 118)  (517 118)  routing T_10_7.sp12_h_r_7 <X> T_10_7.lc_trk_g1_7
 (22 6)  (518 118)  (518 118)  Enable bit of Mux _local_links/g1_mux_7 => sp12_h_r_7 lc_trk_g1_7
 (24 6)  (520 118)  (520 118)  routing T_10_7.sp12_h_r_7 <X> T_10_7.lc_trk_g1_7
 (27 6)  (523 118)  (523 118)  routing T_10_7.lc_trk_g1_7 <X> T_10_7.wire_bram/ram/WDATA_3
 (29 6)  (525 118)  (525 118)  Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_7 wire_bram/ram/WDATA_3
 (30 6)  (526 118)  (526 118)  routing T_10_7.lc_trk_g1_7 <X> T_10_7.wire_bram/ram/WDATA_3
 (37 6)  (533 118)  (533 118)  Enable bit of Mux _out_links/OutMux5_3 => wire_bram/ram/RDATA_3 sp12_h_r_14
 (21 7)  (517 119)  (517 119)  routing T_10_7.sp12_h_r_7 <X> T_10_7.lc_trk_g1_7
 (30 7)  (526 119)  (526 119)  routing T_10_7.lc_trk_g1_7 <X> T_10_7.wire_bram/ram/WDATA_3
 (14 10)  (510 122)  (510 122)  routing T_10_7.sp4_v_t_25 <X> T_10_7.lc_trk_g2_4
 (14 11)  (510 123)  (510 123)  routing T_10_7.sp4_v_t_25 <X> T_10_7.lc_trk_g2_4
 (16 11)  (512 123)  (512 123)  routing T_10_7.sp4_v_t_25 <X> T_10_7.lc_trk_g2_4
 (17 11)  (513 123)  (513 123)  Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_25 lc_trk_g2_4
 (0 14)  (496 126)  (496 126)  routing T_10_7.lc_trk_g2_4 <X> T_10_7.wire_bram/ram/WE
 (1 14)  (497 126)  (497 126)  Enable bit of Mux _global_links/set_rst_mux => lc_trk_g2_4 wire_bram/ram/WE
 (1 15)  (497 127)  (497 127)  routing T_10_7.lc_trk_g2_4 <X> T_10_7.wire_bram/ram/WE


LogicTile_11_7

 (8 1)  (546 113)  (546 113)  routing T_11_7.sp4_h_r_1 <X> T_11_7.sp4_v_b_1
 (13 8)  (551 120)  (551 120)  routing T_11_7.sp4_v_t_45 <X> T_11_7.sp4_v_b_8


IO_Tile_13_7

 (3 1)  (649 113)  (649 113)  IO control bit: IORIGHT_REN_1

 (2 3)  (648 115)  (648 115)  Enable bit of Mux _out_links/OutMux9_0 => wire_io_cluster/io_0/D_IN_0 span4_vert_b_12
 (17 3)  (663 115)  (663 115)  IOB_0 IO Functioning bit
 (2 6)  (648 118)  (648 118)  IO control bit: IORIGHT_REN_0

 (1 9)  (647 121)  (647 121)  Enable bit of Mux _out_links/OutMux1_2 => wire_io_cluster/io_1/D_IN_0 span4_horz_12
 (17 13)  (663 125)  (663 125)  IOB_1 IO Functioning bit


IO_Tile_0_6

 (16 0)  (1 96)  (1 96)  IOB_0 IO Functioning bit
 (3 1)  (14 97)  (14 97)  IO control bit: BIOLEFT_REN_1

 (5 2)  (12 98)  (12 98)  routing T_0_6.span4_vert_b_11 <X> T_0_6.lc_trk_g0_3
 (7 2)  (10 98)  (10 98)  Enable bit of Mux _local_links/g0_mux_3 => span4_vert_b_11 lc_trk_g0_3
 (8 2)  (9 98)  (9 98)  routing T_0_6.span4_vert_b_11 <X> T_0_6.lc_trk_g0_3
 (17 3)  (0 99)  (0 99)  IOB_0 IO Functioning bit
 (12 4)  (5 100)  (5 100)  routing T_0_6.lc_trk_g1_5 <X> T_0_6.wire_io_cluster/io_0/D_OUT_0
 (13 4)  (4 100)  (4 100)  routing T_0_6.lc_trk_g1_5 <X> T_0_6.wire_io_cluster/io_0/D_OUT_0
 (16 4)  (1 100)  (1 100)  IOB_0 IO Functioning bit
 (13 5)  (4 101)  (4 101)  Enable bit of Mux _io_cluster/in_mux0_1 => lc_trk_g1_5 wire_io_cluster/io_0/D_OUT_0
 (2 6)  (15 102)  (15 102)  IO control bit: BIOLEFT_REN_0

 (3 6)  (14 102)  (14 102)  IO control bit: BIOLEFT_IE_1

 (3 9)  (14 105)  (14 105)  IO control bit: BIOLEFT_IE_0

 (16 10)  (1 106)  (1 106)  IOB_1 IO Functioning bit
 (12 11)  (5 107)  (5 107)  routing T_0_6.lc_trk_g0_3 <X> T_0_6.wire_io_cluster/io_1/D_OUT_0
 (13 11)  (4 107)  (4 107)  Enable bit of Mux _io_cluster/in_mux1_1 => lc_trk_g0_3 wire_io_cluster/io_1/D_OUT_0
 (5 12)  (12 108)  (12 108)  routing T_0_6.span12_horz_5 <X> T_0_6.lc_trk_g1_5
 (7 12)  (10 108)  (10 108)  Enable bit of Mux _local_links/g1_mux_5 => span12_horz_5 lc_trk_g1_5
 (8 12)  (9 108)  (9 108)  routing T_0_6.span12_horz_5 <X> T_0_6.lc_trk_g1_5
 (8 13)  (9 109)  (9 109)  routing T_0_6.span12_horz_5 <X> T_0_6.lc_trk_g1_5
 (13 13)  (4 109)  (4 109)  routing T_0_6.span4_horz_19 <X> T_0_6.span4_vert_b_3
 (14 13)  (3 109)  (3 109)  routing T_0_6.span4_horz_19 <X> T_0_6.span4_vert_b_3
 (17 13)  (0 109)  (0 109)  IOB_1 IO Functioning bit
 (16 14)  (1 110)  (1 110)  IOB_1 IO Functioning bit


RAM_Tile_3_6

 (5 10)  (131 106)  (131 106)  routing T_3_6.sp4_h_r_3 <X> T_3_6.sp4_h_l_43
 (4 11)  (130 107)  (130 107)  routing T_3_6.sp4_h_r_3 <X> T_3_6.sp4_h_l_43
 (19 11)  (145 107)  (145 107)  Enable bit of Mux _span_links/cross_mux_vert_10 => sp12_v_b_21 sp4_v_b_22


LogicTile_7_6

 (6 7)  (340 103)  (340 103)  routing T_7_6.sp4_h_r_3 <X> T_7_6.sp4_h_l_38


LogicTile_9_6

 (11 10)  (453 106)  (453 106)  routing T_9_6.sp4_v_b_0 <X> T_9_6.sp4_v_t_45
 (13 10)  (455 106)  (455 106)  routing T_9_6.sp4_v_b_0 <X> T_9_6.sp4_v_t_45


RAM_Tile_10_6

 (7 0)  (503 96)  (503 96)  Ram config bit: MEMT_bram_cbit_1

 (7 1)  (503 97)  (503 97)  Ram config bit: MEMT_bram_cbit_0

 (9 1)  (505 97)  (505 97)  routing T_10_6.sp4_v_t_36 <X> T_10_6.sp4_v_b_1
 (1 2)  (497 98)  (497 98)  routing T_10_6.glb_netwk_4 <X> T_10_6.wire_bram/ram/RCLK
 (2 2)  (498 98)  (498 98)  Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_bram/ram/RCLK
 (7 2)  (503 98)  (503 98)  Ram config bit: MEMT_bram_cbit_3

 (7 3)  (503 99)  (503 99)  Ram config bit: MEMT_bram_cbit_2

 (7 4)  (503 100)  (503 100)  Cascade buffer Enable bit: MEMT_LC01_inmux00_bram_cbit_5

 (15 4)  (511 100)  (511 100)  routing T_10_6.sp4_h_r_1 <X> T_10_6.lc_trk_g1_1
 (16 4)  (512 100)  (512 100)  routing T_10_6.sp4_h_r_1 <X> T_10_6.lc_trk_g1_1
 (17 4)  (513 100)  (513 100)  Enable bit of Mux _local_links/g1_mux_1 => sp4_h_r_1 lc_trk_g1_1
 (7 5)  (503 101)  (503 101)  Cascade bit: MEMT_LC01_inmux00_bram_cbit_4

 (18 5)  (514 101)  (514 101)  routing T_10_6.sp4_h_r_1 <X> T_10_6.lc_trk_g1_1
 (7 6)  (503 102)  (503 102)  Cascade buffer Enable bit: MEMT_LC04_inmux00_bram_cbit_7

 (27 6)  (523 102)  (523 102)  routing T_10_6.lc_trk_g1_1 <X> T_10_6.wire_bram/ram/WDATA_11
 (29 6)  (525 102)  (525 102)  Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_1 wire_bram/ram/WDATA_11
 (36 6)  (532 102)  (532 102)  Enable bit of Mux _out_links/OutMux8_3 => wire_bram/ram/RDATA_11 sp4_h_l_27
 (7 7)  (503 103)  (503 103)  Cascade bit: MEMT_LC04_inmux00_bram_cbit_6

 (3 11)  (499 107)  (499 107)  routing T_10_6.sp12_v_b_1 <X> T_10_6.sp12_h_l_22
 (0 14)  (496 110)  (496 110)  routing T_10_6.lc_trk_g3_5 <X> T_10_6.wire_bram/ram/RE
 (1 14)  (497 110)  (497 110)  Enable bit of Mux _global_links/set_rst_mux => lc_trk_g3_5 wire_bram/ram/RE
 (17 14)  (513 110)  (513 110)  Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_21 lc_trk_g3_5
 (0 15)  (496 111)  (496 111)  routing T_10_6.lc_trk_g3_5 <X> T_10_6.wire_bram/ram/RE
 (1 15)  (497 111)  (497 111)  routing T_10_6.lc_trk_g3_5 <X> T_10_6.wire_bram/ram/RE


LogicTile_11_6

 (10 13)  (548 109)  (548 109)  routing T_11_6.sp4_h_r_5 <X> T_11_6.sp4_v_b_10


IO_Tile_13_6

 (0 0)  (646 96)  (646 96)  Enable bit of Mux _out_links/OutMux2_0 => wire_io_cluster/io_0/D_IN_0 span4_horz_16
 (11 1)  (657 97)  (657 97)  routing T_13_6.span4_vert_t_12 <X> T_13_6.span4_horz_25
 (17 3)  (663 99)  (663 99)  IOB_0 IO Functioning bit
 (2 6)  (648 102)  (648 102)  IO control bit: IORIGHT_REN_0

 (3 6)  (649 102)  (649 102)  IO control bit: IORIGHT_IE_1



IO_Tile_0_5

 (3 6)  (14 86)  (14 86)  IO control bit: BIOLEFT_IE_1

 (3 9)  (14 89)  (14 89)  IO control bit: BIOLEFT_IE_0



LogicTile_1_5



LogicTile_2_5



RAM_Tile_3_5

 (7 1)  (133 81)  (133 81)  Ram config bit: MEMB_Power_Up_Control



LogicTile_4_5



LogicTile_5_5



LogicTile_6_5



LogicTile_7_5



LogicTile_8_5



LogicTile_9_5



RAM_Tile_10_5

 (2 1)  (498 81)  (498 81)  Column buffer control bit: MEMB_colbuf_cntl_1

 (2 2)  (498 82)  (498 82)  Enable bit of Mux _global_links/clk_mux => glb_netwk_1 wire_bram/ram/WCLK
 (14 2)  (510 82)  (510 82)  routing T_10_5.sp4_v_b_12 <X> T_10_5.lc_trk_g0_4
 (0 3)  (496 83)  (496 83)  routing T_10_5.glb_netwk_1 <X> T_10_5.wire_bram/ram/WCLK
 (14 3)  (510 83)  (510 83)  routing T_10_5.sp4_v_b_12 <X> T_10_5.lc_trk_g0_4
 (16 3)  (512 83)  (512 83)  routing T_10_5.sp4_v_b_12 <X> T_10_5.lc_trk_g0_4
 (17 3)  (513 83)  (513 83)  Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_12 lc_trk_g0_4
 (17 4)  (513 84)  (513 84)  Enable bit of Mux _local_links/g1_mux_1 => sp4_r_v_b_25 lc_trk_g1_1
 (18 5)  (514 85)  (514 85)  routing T_10_5.sp4_r_v_b_25 <X> T_10_5.lc_trk_g1_1
 (27 6)  (523 86)  (523 86)  routing T_10_5.lc_trk_g1_1 <X> T_10_5.wire_bram/ram/WDATA_3
 (29 6)  (525 86)  (525 86)  Enable bit of Mux _bram/lcb1_3 => lc_trk_g1_1 wire_bram/ram/WDATA_3
 (40 7)  (536 87)  (536 87)  Enable bit of Mux _out_links/OutMux4_3 => wire_bram/ram/RDATA_3 sp12_v_b_22
 (2 9)  (498 89)  (498 89)  Column buffer control bit: MEMB_colbuf_cntl_4

 (1 14)  (497 94)  (497 94)  Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_bram/ram/WE
 (1 15)  (497 95)  (497 95)  routing T_10_5.lc_trk_g0_4 <X> T_10_5.wire_bram/ram/WE


LogicTile_11_5



LogicTile_12_5



IO_Tile_13_5

 (3 6)  (649 86)  (649 86)  IO control bit: IORIGHT_IE_1

 (3 9)  (649 89)  (649 89)  IO control bit: IORIGHT_IE_0



IO_Tile_0_4

 (16 0)  (1 64)  (1 64)  IOB_0 IO Functioning bit
 (3 1)  (14 65)  (14 65)  IO control bit: BIOLEFT_REN_1

 (5 2)  (12 66)  (12 66)  routing T_0_4.span4_vert_b_11 <X> T_0_4.lc_trk_g0_3
 (7 2)  (10 66)  (10 66)  Enable bit of Mux _local_links/g0_mux_3 => span4_vert_b_11 lc_trk_g0_3
 (8 2)  (9 66)  (9 66)  routing T_0_4.span4_vert_b_11 <X> T_0_4.lc_trk_g0_3
 (17 3)  (0 67)  (0 67)  IOB_0 IO Functioning bit
 (12 4)  (5 68)  (5 68)  routing T_0_4.lc_trk_g1_5 <X> T_0_4.wire_io_cluster/io_0/D_OUT_0
 (13 4)  (4 68)  (4 68)  routing T_0_4.lc_trk_g1_5 <X> T_0_4.wire_io_cluster/io_0/D_OUT_0
 (16 4)  (1 68)  (1 68)  IOB_0 IO Functioning bit
 (13 5)  (4 69)  (4 69)  Enable bit of Mux _io_cluster/in_mux0_1 => lc_trk_g1_5 wire_io_cluster/io_0/D_OUT_0
 (2 6)  (15 70)  (15 70)  IO control bit: BIOLEFT_REN_0

 (3 6)  (14 70)  (14 70)  IO control bit: BIOLEFT_IE_1

 (3 9)  (14 73)  (14 73)  IO control bit: BIOLEFT_IE_0

 (16 10)  (1 74)  (1 74)  IOB_1 IO Functioning bit
 (12 11)  (5 75)  (5 75)  routing T_0_4.lc_trk_g0_3 <X> T_0_4.wire_io_cluster/io_1/D_OUT_0
 (13 11)  (4 75)  (4 75)  Enable bit of Mux _io_cluster/in_mux1_1 => lc_trk_g0_3 wire_io_cluster/io_1/D_OUT_0
 (5 12)  (12 76)  (12 76)  routing T_0_4.span12_horz_5 <X> T_0_4.lc_trk_g1_5
 (7 12)  (10 76)  (10 76)  Enable bit of Mux _local_links/g1_mux_5 => span12_horz_5 lc_trk_g1_5
 (8 12)  (9 76)  (9 76)  routing T_0_4.span12_horz_5 <X> T_0_4.lc_trk_g1_5
 (11 12)  (6 76)  (6 76)  routing T_0_4.span4_horz_19 <X> T_0_4.span4_vert_t_15
 (12 12)  (5 76)  (5 76)  routing T_0_4.span4_horz_19 <X> T_0_4.span4_vert_t_15
 (8 13)  (9 77)  (9 77)  routing T_0_4.span12_horz_5 <X> T_0_4.lc_trk_g1_5
 (17 13)  (0 77)  (0 77)  IOB_1 IO Functioning bit
 (16 14)  (1 78)  (1 78)  IOB_1 IO Functioning bit


LogicTile_1_4



LogicTile_2_4



RAM_Tile_3_4

 (5 10)  (131 74)  (131 74)  routing T_3_4.sp4_h_r_3 <X> T_3_4.sp4_h_l_43
 (4 11)  (130 75)  (130 75)  routing T_3_4.sp4_h_r_3 <X> T_3_4.sp4_h_l_43


LogicTile_4_4



LogicTile_5_4



LogicTile_6_4



LogicTile_7_4

 (9 3)  (343 67)  (343 67)  routing T_7_4.sp4_v_b_5 <X> T_7_4.sp4_v_t_36
 (10 3)  (344 67)  (344 67)  routing T_7_4.sp4_v_b_5 <X> T_7_4.sp4_v_t_36
 (6 7)  (340 71)  (340 71)  routing T_7_4.sp4_h_r_3 <X> T_7_4.sp4_h_l_38


LogicTile_8_4



LogicTile_9_4



RAM_Tile_10_4

 (7 0)  (503 64)  (503 64)  Ram config bit: MEMT_bram_cbit_1

 (14 0)  (510 64)  (510 64)  routing T_10_4.sp12_h_r_0 <X> T_10_4.lc_trk_g0_0
 (7 1)  (503 65)  (503 65)  Ram config bit: MEMT_bram_cbit_0

 (14 1)  (510 65)  (510 65)  routing T_10_4.sp12_h_r_0 <X> T_10_4.lc_trk_g0_0
 (15 1)  (511 65)  (511 65)  routing T_10_4.sp12_h_r_0 <X> T_10_4.lc_trk_g0_0
 (17 1)  (513 65)  (513 65)  Enable bit of Mux _local_links/g0_mux_0 => sp12_h_r_0 lc_trk_g0_0
 (1 2)  (497 66)  (497 66)  routing T_10_4.glb_netwk_4 <X> T_10_4.wire_bram/ram/RCLK
 (2 2)  (498 66)  (498 66)  Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_bram/ram/RCLK
 (7 2)  (503 66)  (503 66)  Ram config bit: MEMT_bram_cbit_3

 (7 3)  (503 67)  (503 67)  Ram config bit: MEMT_bram_cbit_2

 (7 4)  (503 68)  (503 68)  Cascade buffer Enable bit: MEMT_LC01_inmux00_bram_cbit_5

 (7 5)  (503 69)  (503 69)  Cascade bit: MEMT_LC01_inmux00_bram_cbit_4

 (7 6)  (503 70)  (503 70)  Cascade buffer Enable bit: MEMT_LC04_inmux00_bram_cbit_7

 (29 6)  (525 70)  (525 70)  Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_0 wire_bram/ram/WDATA_11
 (36 6)  (532 70)  (532 70)  Enable bit of Mux _out_links/OutMux8_3 => wire_bram/ram/RDATA_11 sp4_h_l_27
 (7 7)  (503 71)  (503 71)  Cascade bit: MEMT_LC04_inmux00_bram_cbit_6

 (3 10)  (499 74)  (499 74)  routing T_10_4.sp12_v_t_22 <X> T_10_4.sp12_h_l_22
 (0 14)  (496 78)  (496 78)  routing T_10_4.lc_trk_g3_5 <X> T_10_4.wire_bram/ram/RE
 (1 14)  (497 78)  (497 78)  Enable bit of Mux _global_links/set_rst_mux => lc_trk_g3_5 wire_bram/ram/RE
 (17 14)  (513 78)  (513 78)  Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_45 lc_trk_g3_5
 (0 15)  (496 79)  (496 79)  routing T_10_4.lc_trk_g3_5 <X> T_10_4.wire_bram/ram/RE
 (1 15)  (497 79)  (497 79)  routing T_10_4.lc_trk_g3_5 <X> T_10_4.wire_bram/ram/RE
 (18 15)  (514 79)  (514 79)  routing T_10_4.sp4_r_v_b_45 <X> T_10_4.lc_trk_g3_5


LogicTile_11_4

 (13 6)  (551 70)  (551 70)  routing T_11_4.sp4_v_b_5 <X> T_11_4.sp4_v_t_40


LogicTile_12_4



IO_Tile_13_4

 (3 1)  (649 65)  (649 65)  IO control bit: IORIGHT_REN_1

 (3 9)  (649 73)  (649 73)  IO control bit: IORIGHT_IE_0

 (16 9)  (662 73)  (662 73)  Enable bit of Mux _out_links/OutMuxa_2 => wire_io_cluster/io_1/D_IN_0 span12_horz_4
 (17 13)  (663 77)  (663 77)  IOB_1 IO Functioning bit


IO_Tile_0_3

 (3 6)  (14 54)  (14 54)  IO control bit: IOLEFT_IE_1

 (3 9)  (14 57)  (14 57)  IO control bit: IOLEFT_IE_0



RAM_Tile_3_3

 (7 1)  (133 49)  (133 49)  Ram config bit: MEMB_Power_Up_Control

 (9 9)  (135 57)  (135 57)  routing T_3_3.sp4_v_t_46 <X> T_3_3.sp4_v_b_7
 (10 9)  (136 57)  (136 57)  routing T_3_3.sp4_v_t_46 <X> T_3_3.sp4_v_b_7


RAM_Tile_10_3

 (2 1)  (498 49)  (498 49)  Column buffer control bit: MEMB_colbuf_cntl_1

 (2 2)  (498 50)  (498 50)  Enable bit of Mux _global_links/clk_mux => glb_netwk_1 wire_bram/ram/WCLK
 (0 3)  (496 51)  (496 51)  routing T_10_3.glb_netwk_1 <X> T_10_3.wire_bram/ram/WCLK
 (27 6)  (523 54)  (523 54)  routing T_10_3.lc_trk_g3_7 <X> T_10_3.wire_bram/ram/WDATA_3
 (28 6)  (524 54)  (524 54)  routing T_10_3.lc_trk_g3_7 <X> T_10_3.wire_bram/ram/WDATA_3
 (29 6)  (525 54)  (525 54)  Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_7 wire_bram/ram/WDATA_3
 (30 6)  (526 54)  (526 54)  routing T_10_3.lc_trk_g3_7 <X> T_10_3.wire_bram/ram/WDATA_3
 (39 6)  (535 54)  (535 54)  Enable bit of Mux _out_links/OutMux3_3 => wire_bram/ram/RDATA_3 sp12_v_t_5
 (30 7)  (526 55)  (526 55)  routing T_10_3.lc_trk_g3_7 <X> T_10_3.wire_bram/ram/WDATA_3
 (2 9)  (498 57)  (498 57)  Column buffer control bit: MEMB_colbuf_cntl_4

 (14 10)  (510 58)  (510 58)  routing T_10_3.sp4_v_t_25 <X> T_10_3.lc_trk_g2_4
 (14 11)  (510 59)  (510 59)  routing T_10_3.sp4_v_t_25 <X> T_10_3.lc_trk_g2_4
 (16 11)  (512 59)  (512 59)  routing T_10_3.sp4_v_t_25 <X> T_10_3.lc_trk_g2_4
 (17 11)  (513 59)  (513 59)  Enable bit of Mux _local_links/g2_mux_4 => sp4_v_t_25 lc_trk_g2_4
 (0 14)  (496 62)  (496 62)  routing T_10_3.lc_trk_g2_4 <X> T_10_3.wire_bram/ram/WE
 (1 14)  (497 62)  (497 62)  Enable bit of Mux _global_links/set_rst_mux => lc_trk_g2_4 wire_bram/ram/WE
 (22 14)  (518 62)  (518 62)  Enable bit of Mux _local_links/g3_mux_7 => sp4_r_v_b_47 lc_trk_g3_7
 (1 15)  (497 63)  (497 63)  routing T_10_3.lc_trk_g2_4 <X> T_10_3.wire_bram/ram/WE
 (21 15)  (517 63)  (517 63)  routing T_10_3.sp4_r_v_b_47 <X> T_10_3.lc_trk_g3_7


LogicTile_11_3

 (6 8)  (544 56)  (544 56)  routing T_11_3.sp4_h_r_1 <X> T_11_3.sp4_v_b_6
 (13 8)  (551 56)  (551 56)  routing T_11_3.sp4_v_t_45 <X> T_11_3.sp4_v_b_8


IO_Tile_13_3

 (3 1)  (649 49)  (649 49)  IO control bit: IORIGHT_REN_1

 (1 9)  (647 57)  (647 57)  Enable bit of Mux _out_links/OutMux1_2 => wire_io_cluster/io_1/D_IN_0 span4_horz_12
 (3 9)  (649 57)  (649 57)  IO control bit: IORIGHT_IE_0

 (17 13)  (663 61)  (663 61)  IOB_1 IO Functioning bit


IO_Tile_0_2

 (5 0)  (12 32)  (12 32)  routing T_0_2.span4_vert_b_1 <X> T_0_2.lc_trk_g0_1
 (7 0)  (10 32)  (10 32)  Enable bit of Mux _local_links/g0_mux_1 => span4_vert_b_1 lc_trk_g0_1
 (16 0)  (1 32)  (1 32)  IOB_0 IO Functioning bit
 (3 1)  (14 33)  (14 33)  IO control bit: BIOLEFT_REN_1

 (8 1)  (9 33)  (9 33)  routing T_0_2.span4_vert_b_1 <X> T_0_2.lc_trk_g0_1
 (17 3)  (0 35)  (0 35)  IOB_0 IO Functioning bit
 (12 4)  (5 36)  (5 36)  routing T_0_2.lc_trk_g1_5 <X> T_0_2.wire_io_cluster/io_0/D_OUT_0
 (13 4)  (4 36)  (4 36)  routing T_0_2.lc_trk_g1_5 <X> T_0_2.wire_io_cluster/io_0/D_OUT_0
 (16 4)  (1 36)  (1 36)  IOB_0 IO Functioning bit
 (13 5)  (4 37)  (4 37)  Enable bit of Mux _io_cluster/in_mux0_1 => lc_trk_g1_5 wire_io_cluster/io_0/D_OUT_0
 (2 6)  (15 38)  (15 38)  IO control bit: BIOLEFT_REN_0

 (3 6)  (14 38)  (14 38)  IO control bit: BIOLEFT_IE_1

 (3 9)  (14 41)  (14 41)  IO control bit: BIOLEFT_IE_0

 (16 10)  (1 42)  (1 42)  IOB_1 IO Functioning bit
 (13 11)  (4 43)  (4 43)  Enable bit of Mux _io_cluster/in_mux1_1 => lc_trk_g0_1 wire_io_cluster/io_1/D_OUT_0
 (5 12)  (12 44)  (12 44)  routing T_0_2.span12_horz_5 <X> T_0_2.lc_trk_g1_5
 (7 12)  (10 44)  (10 44)  Enable bit of Mux _local_links/g1_mux_5 => span12_horz_5 lc_trk_g1_5
 (8 12)  (9 44)  (9 44)  routing T_0_2.span12_horz_5 <X> T_0_2.lc_trk_g1_5
 (8 13)  (9 45)  (9 45)  routing T_0_2.span12_horz_5 <X> T_0_2.lc_trk_g1_5
 (17 13)  (0 45)  (0 45)  IOB_1 IO Functioning bit
 (16 14)  (1 46)  (1 46)  IOB_1 IO Functioning bit


RAM_Tile_3_2

 (3 14)  (129 46)  (129 46)  routing T_3_2.sp12_h_r_1 <X> T_3_2.sp12_v_t_22
 (3 15)  (129 47)  (129 47)  routing T_3_2.sp12_h_r_1 <X> T_3_2.sp12_v_t_22


LogicTile_9_2

 (6 2)  (448 34)  (448 34)  routing T_9_2.sp4_v_b_9 <X> T_9_2.sp4_v_t_37
 (5 3)  (447 35)  (447 35)  routing T_9_2.sp4_v_b_9 <X> T_9_2.sp4_v_t_37


RAM_Tile_10_2

 (7 0)  (503 32)  (503 32)  Ram config bit: MEMT_bram_cbit_1

 (7 1)  (503 33)  (503 33)  Ram config bit: MEMT_bram_cbit_0

 (9 1)  (505 33)  (505 33)  routing T_10_2.sp4_v_t_36 <X> T_10_2.sp4_v_b_1
 (1 2)  (497 34)  (497 34)  routing T_10_2.glb_netwk_4 <X> T_10_2.wire_bram/ram/RCLK
 (2 2)  (498 34)  (498 34)  Enable bit of Mux _global_links/clk_mux => glb_netwk_4 wire_bram/ram/RCLK
 (7 2)  (503 34)  (503 34)  Ram config bit: MEMT_bram_cbit_3

 (7 3)  (503 35)  (503 35)  Ram config bit: MEMT_bram_cbit_2

 (7 5)  (503 37)  (503 37)  Cascade bit: MEMT_LC01_inmux00_bram_cbit_4

 (27 6)  (523 38)  (523 38)  routing T_10_2.lc_trk_g3_1 <X> T_10_2.wire_bram/ram/WDATA_11
 (28 6)  (524 38)  (524 38)  routing T_10_2.lc_trk_g3_1 <X> T_10_2.wire_bram/ram/WDATA_11
 (29 6)  (525 38)  (525 38)  Enable bit of Mux _bram/lcb1_3 => lc_trk_g3_1 wire_bram/ram/WDATA_11
 (37 6)  (533 38)  (533 38)  Enable bit of Mux _out_links/OutMux5_3 => wire_bram/ram/RDATA_11 sp12_h_l_13
 (7 7)  (503 39)  (503 39)  Cascade bit: MEMT_LC04_inmux00_bram_cbit_6

 (3 10)  (499 42)  (499 42)  routing T_10_2.sp12_v_t_22 <X> T_10_2.sp12_h_l_22
 (15 12)  (511 44)  (511 44)  routing T_10_2.sp4_h_l_20 <X> T_10_2.lc_trk_g3_1
 (16 12)  (512 44)  (512 44)  routing T_10_2.sp4_h_l_20 <X> T_10_2.lc_trk_g3_1
 (17 12)  (513 44)  (513 44)  Enable bit of Mux _local_links/g3_mux_1 => sp4_h_l_20 lc_trk_g3_1
 (18 12)  (514 44)  (514 44)  routing T_10_2.sp4_h_l_20 <X> T_10_2.lc_trk_g3_1
 (0 14)  (496 46)  (496 46)  routing T_10_2.lc_trk_g3_5 <X> T_10_2.wire_bram/ram/RE
 (1 14)  (497 46)  (497 46)  Enable bit of Mux _global_links/set_rst_mux => lc_trk_g3_5 wire_bram/ram/RE
 (17 14)  (513 46)  (513 46)  Enable bit of Mux _local_links/g3_mux_5 => sp4_r_v_b_21 lc_trk_g3_5
 (0 15)  (496 47)  (496 47)  routing T_10_2.lc_trk_g3_5 <X> T_10_2.wire_bram/ram/RE
 (1 15)  (497 47)  (497 47)  routing T_10_2.lc_trk_g3_5 <X> T_10_2.wire_bram/ram/RE


LogicTile_12_2

 (5 14)  (597 46)  (597 46)  routing T_12_2.sp4_v_b_9 <X> T_12_2.sp4_h_l_44


IO_Tile_13_2

 (3 6)  (649 38)  (649 38)  IO control bit: BIORIGHT_IE_1

 (3 9)  (649 41)  (649 41)  IO control bit: BIORIGHT_IE_0



IO_Tile_0_1

 (3 6)  (14 22)  (14 22)  IO control bit: BIOLEFT_IE_1

 (3 9)  (14 25)  (14 25)  IO control bit: BIOLEFT_IE_0



RAM_Tile_3_1

 (7 1)  (133 17)  (133 17)  Ram config bit: MEMB_Power_Up_Control

 (3 14)  (129 30)  (129 30)  routing T_3_1.sp12_h_r_1 <X> T_3_1.sp12_v_t_22
 (3 15)  (129 31)  (129 31)  routing T_3_1.sp12_h_r_1 <X> T_3_1.sp12_v_t_22


RAM_Tile_10_1

 (2 2)  (498 18)  (498 18)  Enable bit of Mux _global_links/clk_mux => glb_netwk_1 wire_bram/ram/WCLK
 (14 2)  (510 18)  (510 18)  routing T_10_1.sp4_v_b_12 <X> T_10_1.lc_trk_g0_4
 (0 3)  (496 19)  (496 19)  routing T_10_1.glb_netwk_1 <X> T_10_1.wire_bram/ram/WCLK
 (14 3)  (510 19)  (510 19)  routing T_10_1.sp4_v_b_12 <X> T_10_1.lc_trk_g0_4
 (16 3)  (512 19)  (512 19)  routing T_10_1.sp4_v_b_12 <X> T_10_1.lc_trk_g0_4
 (17 3)  (513 19)  (513 19)  Enable bit of Mux _local_links/g0_mux_4 => sp4_v_b_12 lc_trk_g0_4
 (22 3)  (518 19)  (518 19)  Enable bit of Mux _local_links/g0_mux_6 => sp4_r_v_b_30 lc_trk_g0_6
 (25 3)  (521 19)  (521 19)  routing T_10_1.sp4_r_v_b_30 <X> T_10_1.lc_trk_g0_6
 (29 6)  (525 22)  (525 22)  Enable bit of Mux _bram/lcb1_3 => lc_trk_g0_6 wire_bram/ram/WDATA_3
 (30 6)  (526 22)  (526 22)  routing T_10_1.lc_trk_g0_6 <X> T_10_1.wire_bram/ram/WDATA_3
 (37 6)  (533 22)  (533 22)  Enable bit of Mux _out_links/OutMux5_3 => wire_bram/ram/RDATA_3 sp12_h_r_14
 (30 7)  (526 23)  (526 23)  routing T_10_1.lc_trk_g0_6 <X> T_10_1.wire_bram/ram/WDATA_3
 (1 14)  (497 30)  (497 30)  Enable bit of Mux _global_links/set_rst_mux => lc_trk_g0_4 wire_bram/ram/WE
 (1 15)  (497 31)  (497 31)  routing T_10_1.lc_trk_g0_4 <X> T_10_1.wire_bram/ram/WE


IO_Tile_13_1

 (3 6)  (649 22)  (649 22)  IO control bit: BIORIGHT_IE_1

 (3 9)  (649 25)  (649 25)  IO control bit: BIORIGHT_IE_0



GlobalNetwork_0_0

 (1 1)  (331 142)  (331 142)  routing T_0_0.padin_1 <X> T_0_0.glb_netwk_1
 (0 2)  (330 145)  (330 145)  routing T_0_0.padin_4 <X> T_0_0.glb_netwk_4


IO_Tile_1_0

 (3 6)  (45 8)  (45 8)  IO control bit: BIODOWN_IE_1

 (3 9)  (45 6)  (45 6)  IO control bit: BIODOWN_IE_0



IO_Tile_2_0

 (3 6)  (99 8)  (99 8)  IO control bit: BIODOWN_IE_1

 (3 9)  (99 6)  (99 6)  IO control bit: BIODOWN_IE_0



IO_Tile_3_0

 (12 2)  (160 12)  (160 12)  routing T_3_0.span4_vert_31 <X> T_3_0.span4_horz_l_13
 (3 6)  (153 8)  (153 8)  IO control bit: BIODOWN_IE_1

 (3 9)  (153 6)  (153 6)  IO control bit: BIODOWN_IE_0



IO_Tile_4_0

 (3 6)  (195 8)  (195 8)  IO control bit: BIODOWN_IE_1

 (3 9)  (195 6)  (195 6)  IO control bit: BIODOWN_IE_0



IO_Tile_5_0

 (3 6)  (249 8)  (249 8)  IO control bit: BIODOWN_IE_1

 (3 9)  (249 6)  (249 6)  IO control bit: BIODOWN_IE_0



IO_Tile_6_0

 (3 1)  (303 14)  (303 14)  IO control bit: GIODOWN1_REN_1

 (3 9)  (303 6)  (303 6)  IO control bit: GIODOWN1_IE_0



IO_Tile_7_0

 (3 1)  (361 14)  (361 14)  IO control bit: GIODOWN0_REN_1

 (0 3)  (357 13)  (357 13)  Enable bit of Mux _out_links/OutMux5_0 => wire_io_cluster/io_0/D_IN_0 span4_vert_40
 (17 3)  (339 13)  (339 13)  IOB_0 IO Functioning bit
 (3 9)  (361 6)  (361 6)  IO control bit: GIODOWN0_IE_0

 (17 9)  (339 6)  (339 6)  Enable bit of Mux _out_links/OutMuxb_2 => wire_io_cluster/io_1/D_IN_0 span12_vert_12
 (17 13)  (339 2)  (339 2)  IOB_1 IO Functioning bit


IO_Tile_8_0

 (3 6)  (415 8)  (415 8)  IO control bit: IODOWN_IE_1

 (3 9)  (415 6)  (415 6)  IO control bit: IODOWN_IE_0



IO_Tile_9_0

 (3 1)  (469 14)  (469 14)  IO control bit: IODOWN_REN_1

 (0 8)  (465 7)  (465 7)  Enable bit of Mux _out_links/OutMux2_2 => wire_io_cluster/io_1/D_IN_0 span4_vert_20
 (3 9)  (469 6)  (469 6)  IO control bit: IODOWN_IE_0

 (17 13)  (447 2)  (447 2)  IOB_1 IO Functioning bit


IO_Tile_10_0

 (17 3)  (501 13)  (501 13)  IOB_0 IO Functioning bit
 (17 5)  (501 10)  (501 10)  Enable bit of Mux _out_links/OutMuxc_0 => wire_io_cluster/io_0/D_IN_0 span12_vert_16
 (2 6)  (522 8)  (522 8)  IO control bit: IODOWN_REN_0

 (3 6)  (523 8)  (523 8)  IO control bit: IODOWN_IE_1



IO_Tile_11_0

 (3 1)  (565 14)  (565 14)  IO control bit: IODOWN_REN_1

 (0 3)  (561 13)  (561 13)  Enable bit of Mux _out_links/OutMux5_0 => wire_io_cluster/io_0/D_IN_0 span4_vert_40
 (17 3)  (543 13)  (543 13)  IOB_0 IO Functioning bit
 (2 6)  (564 8)  (564 8)  IO control bit: IODOWN_REN_0

 (16 8)  (542 7)  (542 7)  Enable bit of Mux _out_links/OutMuxc_2 => wire_io_cluster/io_1/D_IN_0 span12_vert_20
 (17 13)  (543 2)  (543 2)  IOB_1 IO Functioning bit


IO_Tile_12_0

 (3 1)  (619 14)  (619 14)  IO control bit: BIODOWN_REN_1

 (0 8)  (615 7)  (615 7)  Enable bit of Mux _out_links/OutMux2_2 => wire_io_cluster/io_1/D_IN_0 span4_vert_20
 (3 9)  (619 6)  (619 6)  IO control bit: BIODOWN_IE_0

 (17 13)  (597 2)  (597 2)  IOB_1 IO Functioning bit

